[U-Boot] [PATCH v4 1/7] driver/ddr: Add support for setting timing in hws_topology_map

[Chris Packham]

Hi Marek,

On Sat, Jun 10, 2017 at 5:28 AM, Marek Behún <marek.behun at nic.cz> wrote:
> The DDR3 training code for Marvell A38X currently computes 1t timing
> when given board topology map of the Turris Omnia, but Omnia needs 2t.
>
> This patch adds support for enforcing the 2t timing in struct
> hws_topology_map, through a new enum hws_timing, which can assume
> following values:
>   HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
>                     from the number of CSs
>   HWS_TIM_1T      - enforce 1t
>   HWS_TIM_2T      - enforce 2t
>
> This patch also sets all the board topology maps (db-88f6820-amc,
> db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
> HWS_TIM_DEFAULT.
>
> Signed-off-by: Marek Behun <marek.behun at nic.cz>
> Reviewed-by: Stefan Roese <sr at denx.de>

Sorry for only noticing this now but I'd like to add to this
discussion that Marvell _unconditionally_ enable 2T mode in their
bootloader (personally I hope they adopt your change). This may be an
indication that we should set HWS_TIM_2T for the clearfog and
db-88f6820 boards.