[U-Boot] [PATCH v3 4/6] am335x-fb: setup display PLL

[Anatolij Gustschin]

On Tue,  9 Jan 2018 19:01:34 +0100
Hannes Schmelzer oe5hpm at oevsv.at wrote:

> The LCDC IP-core an be feed from several clock sources, one of those is
> a dedicated DPLL for generating a dividable base-clock for this IP-core.
> 
> The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
> so we must not exceed this value with the PLL frequency (which can lock
> much higher).
> 
> This patch tries every combination of multipliers and divisors of the
> PLL and the IP-core itself for getting as near as possible the the
> requested panel->pxl_clk.
> 
> Signed-off-by: Hannes Schmelzer <oe5hpm at oevsv.at>

Reviewed-by: Anatolij Gustschin <agust at denx.de>