[U-Boot] [PATCH 2/5] zynq: Rework FPGA initialization
Ezequiel Garcia
ezequiel at vanguardiasur.com.ar
Wed Jan 17 13:56:23 UTC 2018
This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.
Also, the implementation is reworked to be cleaner
and a bit smaller.
add/remove: 2/11 grow/shrink: 0/1 up/down: 420/-608 (-188)
function old new delta
zynq_fpga_descs - 352 +352
zynq_fpga_desc - 68 +68
fpga100 28 - -28
fpga045 28 - -28
fpga035 28 - -28
fpga030 28 - -28
fpga020 28 - -28
fpga015 28 - -28
fpga014s 28 - -28
fpga012s 28 - -28
fpga010 28 - -28
fpga007s 28 - -28
fpga 28 - -28
board_init 332 32 -300
Total: Before=574182, After=573994, chg -0.03%
Signed-off-by: Ariel D'Alessandro <ariel at vanguardiasur.com.ar>
Signed-off-by: Ezequiel Garcia <ezequiel at vanguardiasur.com.ar>
---
arch/arm/mach-zynq/cpu.c | 41 +++++++++++++++++++-
arch/arm/mach-zynq/include/mach/sys_proto.h | 3 ++
board/xilinx/zynq/board.c | 59 +----------------------------
3 files changed, 44 insertions(+), 59 deletions(-)
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index ee1c1a943b66..53a07b0059c2 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -5,14 +5,36 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <zynqpl.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
-#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/ps7_init_gpl.h>
+#include <asm/arch/sys_proto.h>
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static const struct {
+ u8 idcode;
+ xilinx_desc desc;
+} zynq_fpga_descs[] = {
+ { .idcode = XILINX_ZYNQ_7007S, .desc = XILINX_XC7Z007S_DESC(0x07) },
+ { .idcode = XILINX_ZYNQ_7010, .desc = XILINX_XC7Z010_DESC(0x10) },
+ { .idcode = XILINX_ZYNQ_7012S, .desc = XILINX_XC7Z012S_DESC(0x12) },
+ { .idcode = XILINX_ZYNQ_7014S, .desc = XILINX_XC7Z014S_DESC(0x14) },
+ { .idcode = XILINX_ZYNQ_7015, .desc = XILINX_XC7Z015_DESC(0x15) },
+ { .idcode = XILINX_ZYNQ_7020, .desc = XILINX_XC7Z020_DESC(0x20) },
+ { .idcode = XILINX_ZYNQ_7030, .desc = XILINX_XC7Z030_DESC(0x30) },
+ { .idcode = XILINX_ZYNQ_7035, .desc = XILINX_XC7Z035_DESC(0x35) },
+ { .idcode = XILINX_ZYNQ_7045, .desc = XILINX_XC7Z045_DESC(0x45) },
+ { .idcode = XILINX_ZYNQ_7100, .desc = XILINX_XC7Z100_DESC(0x100) },
+ { /* Sentinel */ },
+};
+#endif
+
int arch_cpu_init(void)
{
zynq_slcr_unlock();
@@ -60,3 +82,20 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+const xilinx_desc *zynq_fpga_desc(void)
+{
+ u32 idcode;
+ u8 i;
+
+ idcode = zynq_slcr_get_idcode();
+ for (i = 0; zynq_fpga_descs[i].idcode; i++) {
+ if (zynq_fpga_descs[i].idcode == idcode) {
+ return &zynq_fpga_descs[i].desc;
+ }
+ }
+ return NULL;
+}
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
index af61352dd110..fd5744c4e85e 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -7,6 +7,8 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <xilinx.h>
+
extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
@@ -16,6 +18,7 @@ extern u32 zynq_slcr_get_boot_mode(void);
extern u32 zynq_slcr_get_idcode(void);
extern int zynq_slcr_get_mio_pin_status(const char *periph);
extern void zynq_ddrc_init(void);
+extern const xilinx_desc *zynq_fpga_desc(void);
extern unsigned int zynq_get_silicon_version(void);
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index e59038106aa6..f9e7bca4ee40 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -15,69 +15,12 @@
DECLARE_GLOBAL_DATA_PTR;
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static xilinx_desc fpga;
-
-/* It can be done differently */
-static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
-static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
-static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
-static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
-static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
-#endif
-
int board_init(void)
{
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
- u32 idcode;
-
- idcode = zynq_slcr_get_idcode();
-
- switch (idcode) {
- case XILINX_ZYNQ_7007S:
- fpga = fpga007s;
- break;
- case XILINX_ZYNQ_7010:
- fpga = fpga010;
- break;
- case XILINX_ZYNQ_7012S:
- fpga = fpga012s;
- break;
- case XILINX_ZYNQ_7014S:
- fpga = fpga014s;
- break;
- case XILINX_ZYNQ_7015:
- fpga = fpga015;
- break;
- case XILINX_ZYNQ_7020:
- fpga = fpga020;
- break;
- case XILINX_ZYNQ_7030:
- fpga = fpga030;
- break;
- case XILINX_ZYNQ_7035:
- fpga = fpga035;
- break;
- case XILINX_ZYNQ_7045:
- fpga = fpga045;
- break;
- case XILINX_ZYNQ_7100:
- fpga = fpga100;
- break;
- }
-#endif
-
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init();
- fpga_add(fpga_xilinx, &fpga);
+ fpga_add(fpga_xilinx, (void *)zynq_fpga_desc());
#endif
return 0;
--
2.15.1
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