[U-Boot] [PATCH 4/7] mmc: uniphier-sd: Handle Renesas div-by-1

[Masahiro Yamada]

2018-01-17 2:17 GMT+09:00 Marek Vasut <marek.vasut at gmail.com>:
> On the Renesas version of the IP, the /1 divider is realized by
> setting the clock register [7:0] to 0xff instead of setting bit
> 10 of the register. Check the quirk and handle accordingly.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas at gmail.com>
> Cc: Jaehoon Chung <jh80.chung at samsung.com>
> Cc: Masahiro Yamada <yamada.masahiro at socionext.com>
> ---
>  drivers/mmc/uniphier-sd.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index 2f7ec680a3..d828535b11 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -75,6 +75,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define   UNIPHIER_SD_CLKCTL_DIV4      BIT(0)  /* SDCLK = CLK / 4 */
>  #define   UNIPHIER_SD_CLKCTL_DIV2      0       /* SDCLK = CLK / 2 */
>  #define   UNIPHIER_SD_CLKCTL_DIV1      BIT(10) /* SDCLK = CLK */
> +#define   UNIPHIER_SD_CLKCTL_RCAR_DIV1 0xff    /* SDCLK = CLK (RCar ver.) */
>  #define   UNIPHIER_SD_CLKCTL_OFFEN     BIT(9)  /* stop SDCLK when unused */
>  #define   UNIPHIER_SD_CLKCTL_SCLKEN    BIT(8)  /* SDCLK output enable */
>  #define UNIPHIER_SD_SIZE               0x04c   /* block size */
> @@ -641,7 +642,8 @@ static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
>         divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
>
>         if (divisor <= 1)
> -               val = UNIPHIER_SD_CLKCTL_DIV1;
> +               val = (priv->caps & UNIPHIER_SD_CAP_RCAR) ?
> +                     UNIPHIER_SD_CLKCTL_RCAR_DIV1 : UNIPHIER_SD_CLKCTL_DIV1;
>         else if (divisor <= 2)
>                 val = UNIPHIER_SD_CLKCTL_DIV2;
>         else if (divisor <= 4)
> --
> 2.15.1


Acked-by: Masahiro Yamada <yamada.masahiro at socionext.com>

-- 
Best Regards
Masahiro Yamada