[U-Boot] [PATCH 4/6] Add DTS for Broadwell-DE platform board
vnktux
vnktux at protonmail.com
Fri Jan 26 11:21:12 UTC 2018
This patch include a DTS file for a Broadwell-de platform used for developing called Poseidon. I did not include the 3 microcodes to keep the patch small, do I have to submit them as well?
Signed-off-by: Vincenzo Bove <vnktux at protonmail.com>
---
arch/x86/dts/Makefile | 1 +
arch/x86/dts/poseidon.dts | 177 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 178 insertions(+)
create mode 100644 arch/x86/dts/poseidon.dts
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 6d0c4b65ec..e59f192b6e 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -15,6 +15,7 @@ dtb-y += bayleybay.dtb \
efi.dtb \
galileo.dtb \
minnowmax.dtb \
+ poseidon.dtb \
qemu-x86_i440fx.dtb \
qemu-x86_q35.dtb \
theadorable-x86-dfi-bt700.dtb \
diff --git a/arch/x86/dts/poseidon.dts b/arch/x86/dts/poseidon.dts
new file mode 100644
index 0000000000..3a08dc76df
--- /dev/null
+++ b/arch/x86/dts/poseidon.dts
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn at gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <asm/arch-broadwell-de/fsp/fsp_configs.h>
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
+
+/ {
+ model = "Intel Broadwell-DE";
+ compatible = "x86", "intel,poseidon", "intel,broadwell-de";
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ tsc-timer {
+ clock-frequency = <1000000000>;
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+ pch at 1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /*PCI_BDF(0, 31, 0) LPC Controller does not generate an interrupt */
+ PCI_BDF(0, 31, 2) INTB PIRQB /* SATA Controller #1 */
+ PCI_BDF(0, 31, 3) INTC PIRQC /* SMBus Controller */
+ PCI_BDF(0, 31, 5) INTB PIRQB /* SATA Controller #2 */
+ PCI_BDF(0, 31, 6) INTC PIRQC /* Thermal Subsystem */
+ PCI_BDF(0, 29, 0) INTA PIRQA /* USB EHCI Controller #1 */
+ PCI_BDF(0, 28, 0) INTA PIRQA /* PCI Express Port 1 */
+ PCI_BDF(0, 28, 1) INTB PIRQB /* PCI Express Port 2 */
+ PCI_BDF(0, 28, 2) INTC PIRQC /* PCI Express Port 3 */
+ PCI_BDF(0, 28, 3) INTD PIRQD /* PCI Express Port 4 */
+ PCI_BDF(0, 28, 4) INTA PIRQA /* PCI Express Port 5 */
+ PCI_BDF(0, 28, 5) INTB PIRQB /* PCI Express Port 6 */
+ PCI_BDF(0, 28, 6) INTC PIRQC /* PCI Express Port 7 */
+ PCI_BDF(0, 28, 7) INTD PIRQD /* PCI Express Port 8 */
+ PCI_BDF(0, 25, 0) INTA PIRQA /* Gigabit Ethernet Controller*/
+ PCI_BDF(0, 22, 0) INTA PIRQA /* Intel Management Engine Interface #1 */
+ PCI_BDF(0, 22, 1) INTB PIRQB /* Intel Management Engine Interface #2*/
+ PCI_BDF(0, 22, 2) INTC PIRQC /* IDE-R*/
+ PCI_BDF(0, 22, 3) INTD PIRQD /* KT*/
+ PCI_BDF(0, 20, 0) INTA PIRQA /* xHCI Controller */
+ >;
+ };
+
+ };
+ };
+
+ fsp {
+ compatible = "intel,broadwell-de-fsp";
+ fsp,memEccSupport = <MEM_ECC_SUPPORT_AUTO>;
+ fsp,memDdrMemoryType = <MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM>;
+ fsp,memRankMultiplication = <MEM_RANK_MULTIPLICATION_AUTO>;
+ fsp,memRankMarginTool = <MEM_RANK_MARGIN_TOOL_AUTO>;
+ fsp,memScrambling = <MEM_SCRAMBLING_AUTO>;
+ fsp,memRefreshMode = <MEM_REFRESH_MODE_ACC_SELF_REFRESH>;
+ fsp,memMcOdtOverride = <MEM_MC0DT_OVERRIDE_AUTO>;
+ fsp,memCAParity = <MEM_CA_PARITY_AUTO>;
+ fsp,memThermalThrottling = <MEM_THERMAL_THROTTLING_CLOSEDLOOP>;
+ fsp,memPowerSavingsMode = <MEM_POWER_SAVINGS_MODE_AUTO>;
+ fsp,memElectricalThrottling = <MEM_ELECTRICAL_THROTTLING_DISABLED>;
+ fsp,memPagePolicy = <MEM_PAGE_POLICY_AUTO>;
+ fsp,memSocketInterleaveBelow4G = <MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED>;
+ fsp,memChannelInterleave = <MEM_CHANNEL_INTERLEAVE_AUTO>;
+ fsp,memRankInterleave = <MEM_RANK_INTERLEAVE_AUTO>;
+
+ #ifdef CONFIG_FSP_MEMORY_DOWN
+ fsp,memDownEnable;
+ fsp,memDownCh0Dimm0SpdPtr = <CONFIG_SPD_ADDR>;
+ fsp,memDownCh0Dimm1SpdPtr = <0x0>;
+ fsp,memDownCh1Dimm0SpdPtr = <0x0>;
+ fsp,memDownCh1Dimm1SpdPtr = <0x0>;
+ #endif
+
+ /*#ifdef CONFIG_ENABLE_MRC_CACHE
+ fsp,mem-fast-boot = <MEM_FAST_BOOT_ENABLE>;
+ #else
+ fsp,mem-fast-boot = <MEM_FAST_BOOT_DISABLE>;
+ #endif*/
+ fsp,mem-fast-boot = <MEM_FAST_BOOT_DISABLE>;
+
+ fsp,pam0-hienable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam1-loenable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam1-hienable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam2-loenable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam2-hienable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam3-loenable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam3-hienable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam4-loenable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam4-hienable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam5-loenable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam5-hienable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam6-loenable = <PAM_RW_DRAM_ONLY>;
+ fsp,pam6-hienable = <PAM_RW_DRAM_ONLY>;
+ fsp,memAdr = <MEM_ADR_DISABLED>;
+ fsp,serial-port-type = <SERIAL_PORT_TYPE_IO>;
+ fsp,serial-port-address = <0x3f8>;
+ fsp,serial-port-configure;
+ fsp,serial-port-baudrate = <SERIAL_PORT_BAUDRATE_115200>;
+ fsp,serial-port-controller-init0;
+ fsp,serial-port-controller-init1;
+ fsp,config-iou1-pci-port3 = <CONFIG_IOU1_PCI_PORT3_X4X4X4X4>;
+ fsp,config-iou2-pci-port1 = <CONFIG_IOU2_PCI_PORT1_XXX8>;
+ fsp,pch-pci-port1;
+ fsp,pch-pci-port2;
+ fsp,pch-pci-port3;
+ fsp,pch-pci-port4;
+ fsp,pch-pci-port5;
+ fsp,pch-pci-port6;
+ fsp,pch-pci-port7;
+ fsp,pch-pci-port8;
+ fsp,ehci1-enable;
+ fsp,hyper-threading;
+ fsp,debug-output-level = <DEBUG_OUTPUT_LEVEL_NORMAL>;
+ fsp,tco-timer-halt-lock;
+ fsp,turbo-mode;
+ fsp,boot-perf-mode;
+ fsp,pcie-port1a-aspm = <PCIE_ASPM_DISABLED>;
+ fsp,pcie-port1b-aspm = <PCIE_ASPM_DISABLED>;
+ fsp,pcie-port3a-aspm = <PCIE_ASPM_DISABLED>;
+ fsp,pcie-port3b-aspm = <PCIE_ASPM_DISABLED>;
+ fsp,pcie-port3c-aspm = <PCIE_ASPM_DISABLED>;
+ fsp,pcie-port3d-aspm = <PCIE_ASPM_DISABLED>;
+ fsp,pch-pcie-port1-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,pch-pcie-port2-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,pch-pcie-port3-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,pch-pcie-port4-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,pch-pcie-port5-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,pch-pcie-port6-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,pch-pcie-port7-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,pch-pcie-port8-aspm = <PCH_PCI_ASPM_DISABLED>;
+ fsp,thermal-device-enable;
+ };
+
+ microcode {
+ update at 0 {
+#include "microcode/broadwell_de_microcode/m1050663_0700000e.dtsi"
+ };
+ update at 1 {
+#include "microcode/broadwell_de_microcode/m1050662_00000011.dtsi"
+ };
+ update at 2 {
+#include "microcode/broadwell_de_microcode/mff50661_f1000008.dtsi"
+ };
+ };
+
+};
--
2.11.0
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