[U-Boot] [PATCH 2/6] Add Broadwell-DE include header files
vnktux
vnktux at protonmail.com
Fri Jan 26 11:17:43 UTC 2018
This patch contain all the include headers for Broadwell-DE architecture.
Signed-off-by: Vincenzo Bove <vnktux at protonmail.com>
---
.../asm/arch-broadwell-de/acpi/global_nvs.asl | 15 +
.../asm/arch-broadwell-de/acpi/irq_helper.h | 36 ++
.../asm/arch-broadwell-de/acpi/irqlinks.asl | 454 ++++++++++++++++++++
.../asm/arch-broadwell-de/acpi/irqroute.asl | 29 ++
.../include/asm/arch-broadwell-de/acpi/irqroute.h | 31 ++
.../x86/include/asm/arch-broadwell-de/acpi/lpc.asl | 81 ++++
.../include/asm/arch-broadwell-de/acpi/pcie1.asl | 455 +++++++++++++++++++++
.../asm/arch-broadwell-de/acpi/platform.asl | 61 +++
.../asm/arch-broadwell-de/acpi/southcluster.asl | 339 +++++++++++++++
arch/x86/include/asm/arch-broadwell-de/device.h | 116 ++++++
.../asm/arch-broadwell-de/fsp/fsp_configs.h | 134 ++++++
.../include/asm/arch-broadwell-de/fsp/fsp_vpd.h | 116 ++++++
.../x86/include/asm/arch-broadwell-de/global_nvs.h | 21 +
arch/x86/include/asm/arch-broadwell-de/iomap.h | 58 +++
arch/x86/include/asm/arch-broadwell-de/irq.h | 88 ++++
15 files changed, 2034 insertions(+)
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/device.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/global_nvs.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/iomap.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/irq.h
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl
new file mode 100644
index 0000000000..a28d4dfade
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn at gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+ Offset (0x00),
+ PCNT, 8, /* processor count */
+ IURE, 8, /* internal UART enabled */
+}
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h
new file mode 100644
index 0000000000..5bdddd7d9c
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef ACPI_DEV_IRQ
+#undef PCI_DEV_PIRQ_ROUTE
+#undef PIRQ_PIC_ROUTES
+#undef PIRQ_PIC
+#undef IRQROUTE_H
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ { Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } }
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ { Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } }
+
+#endif
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+ { ACPI_DEV_IRQ(dev_, 0, a_), \
+ ACPI_DEV_IRQ(dev_, 1, b_), \
+ ACPI_DEV_IRQ(dev_, 2, c_), \
+ ACPI_DEV_IRQ(dev_, 3, d_) }
+
+/* Empty PIRQ_PIC definition. */
+#define PIRQ_PIC(pirq_, pic_irq_)
+
+///* Include the mainboard irq route definition */
+#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl
new file mode 100644
index 0000000000..36942982c8
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OperationRegion (PRR0, PCI_Config, 0x00, 0x100)
+Field (PRR0, AnyAcc, NoLock, Preserve) {
+ Offset(0x60),
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8,
+ Offset(0x68),
+ PIRE, 8,
+ PIRF, 8,
+ PIRG, 8,
+ PIRH, 8
+}
+
+Device (LNKA) { // PCI IRQ link A
+ Name (_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 1)
+ Method (_STA,0,NotSerialized) {
+ If(And(PIRA, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRA, 0x80, PIRA)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And(PIRA, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)){
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRA)
+ } // End of _SRS Method
+}
+
+Device(LNKB) { // PCI IRQ link B
+ Name (_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 2)
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRB, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRB, 0x80,PIRB)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRB, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS,
+ ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual(IRQW,Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRB)
+ } // End of _SRS Method
+}
+
+Device(LNKC) { // PCI IRQ link C
+ Name(_HID, EISAID("PNP0C0F"))
+ //Name(_UID, 3)
+
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRC, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or (PIRC, 0x80, PIRC)
+ }
+
+ Method (_CRS, 0, Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRC, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And (PIRC,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRC)
+ } // End of _SRS Method
+}
+
+Device (LNKD) { // PCI IRQ link D
+ Name (_HID,EISAID ("PNP0C0F"))
+
+ //Name(_UID, 4)
+
+ Method (_STA, 0, NotSerialized) {
+ If (And (PIRD, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or(PIRD, 0x80,PIRD)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRD, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRD,0x0F), IRQW)
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW, Local0)// Set IRQ
+ If (LNotEqual (IRQW, Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store(Local0, PIRD)
+ } // End of _SRS Method
+}
+
+Device(LNKE) { // PCI IRQ link E
+ Name(_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 5)
+
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRE, 0x80)) {
+ Return(0x9)
+ } Else {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRE, 0x80, PIRE)
+ }
+
+ Method (_CRS, 0, Serialized) {
+ Name (BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRE, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One, Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRE,0x0F), IRQW)
+ Return (BUF0) // Return Buf0
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW, Local0) // Set IRQ
+ If (LNotEqual (IRQW, Zero)) {
+ And (Local0, 0x7F, Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRE)
+ } // End of _SRS Method
+}
+
+Device(LNKF) { // PCI IRQ link F
+ Name (_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 6)
+
+ Method (_STA,0,NotSerialized) {
+ If (And (PIRF, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or (PIRB, 0x80, PIRF)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRF, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One, Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0, And (PIRF, 0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80, Local0)
+ }
+ Store (Local0, PIRF)
+ } // End of _SRS Method
+}
+
+Device(LNKG) { // PCI IRQ link G
+ Name(_HID,EISAID("PNP0C0F"))
+ //Name(_UID, 7)
+ Method(_STA,0,NotSerialized) {
+ If (And (PIRG, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xB)
+ } // Don't display
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Or(PIRG, 0x80,PIRG)
+ }
+
+ Method (_CRS,0,Serialized){
+ Name(BUF0,ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And(PIRG, 0x80)) {
+ Store(Zero, Local0)
+ } Else {
+ Store(One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And(PIRG,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name (_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit(IRQW,Local0) // Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRG)
+ } // End of _SRS Method
+}
+
+Device(LNKH) { // PCI IRQ link H
+ Name (_HID,EISAID("PNP0C0F"))
+
+ //Name(_UID, 8)
+
+ Method (_STA,0,NotSerialized) {
+ If (And(PIRH, 0x80)) {
+ Return(0x9)
+ } Else {
+ Return(0xB)
+ } // Don't display
+ }
+
+ Method (_DIS,0,NotSerialized) {
+ Or(PIRH, 0x80,PIRH)
+ }
+
+ Method (_CRS,0,Serialized) {
+ Name(BUF0, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){0}})
+ //
+ // Define references to buffer elements
+ //
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low
+ //
+ // Write current settings into IRQ descriptor
+ //
+ If (And (PIRH, 0x80)) {
+ Store (Zero, Local0)
+ } Else {
+ Store (One,Local0)
+ }
+ //
+ // Shift 1 by value in register 70, Save in buffer
+ //
+ ShiftLeft (Local0,And(PIRH,0x0F),IRQW)
+ Return (BUF0)
+ } // End of _CRS method
+
+ Name(_PRS, ResourceTemplate()
+ {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
+
+ Method (_SRS,1,NotSerialized) {
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low
+ FindSetRightBit (IRQW,Local0)// Set IRQ
+ If (LNotEqual (IRQW,Zero)) {
+ And (Local0, 0x7F,Local0)
+ Decrement (Local0)
+ } Else {
+ Or (Local0, 0x80,Local0)
+ }
+ Store (Local0, PIRH)
+ }
+}
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl
new file mode 100644
index 0000000000..39c7a19349
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* PCI Interrupt Routing */
+Method(_PRT)
+{
+ /*
+ * PICM comes from _PIC, which returns the following:
+ * 0 - PIC mode
+ * 1 - APIC mode
+ * 2 - SAPIC mode
+ */
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ }
+}
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h
new file mode 100644
index 0000000000..27701db790
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D)
+
+/*
+* Route each PIRQ[A-H] to a PIC IRQ[0-15]
+* Reserved: 0, 1, 2, 8, 13
+* ACPI/SCI: 9
+*/
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, 5), \
+ PIRQ_PIC(B, 6), \
+ PIRQ_PIC(C, 7), \
+ PIRQ_PIC(D, 10), \
+ PIRQ_PIC(E, 11), \
+ PIRQ_PIC(F, 12), \
+ PIRQ_PIC(G, 14), \
+ PIRQ_PIC(H, 15)
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl
new file mode 100644
index 0000000000..c1a9e2fb7d
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPC0)
+{
+ Name(_ADR, 0x001f0000)
+
+ #include "irqlinks.asl"
+
+ Device (FWH) // Firmware Hub
+ {
+ Name (_HID, EISAID("INT0800"))
+ Name (_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+ })
+ }
+
+ Device (HPET)
+ {
+ Name (_HID, EISAID("PNP0103"))
+ Name (_CID, 0x010CD041)
+
+ Method (_STA, 0) // Device Status
+ {
+ Return (0xf) // Enable and show device
+ }
+
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xfed00000, 0x400)
+ })
+ }
+
+ Device(LDRC) // LPC device: Resource consumption
+ {
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, 2)
+
+ Name (RBUF, ResourceTemplate()
+ {
+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Return (RBUF)
+ }
+ }
+
+ Device (RTC) // Real Time Clock
+ {
+ Name (_HID, EISAID("PNP0B00"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x70, 0x70, 1, 8)
+ })
+ }
+
+ Device (TIMR) // Intel 8254 timer
+ {
+ Name(_HID, EISAID("PNP0100"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags() {0}
+ })
+ }
+}
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl
new file mode 100644
index 0000000000..4c0cd37f50
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl
@@ -0,0 +1,455 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name (PR01, Package() {
+ // [SL01]: PCI Express Slot 1 on 1A on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR01, Package() {
+ // [SL01]: PCI Express Slot 1 on 1A on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH01, Package() {
+ // [SL01]: PCI Express Slot 1 on 1A on PCI0
+ Package() { 0x0000FFFF, 0, 0, 26 },
+ Package() { 0x0000FFFF, 1, 0, 28 },
+ Package() { 0x0000FFFF, 2, 0, 29 },
+ Package() { 0x0000FFFF, 3, 0, 30 },
+})
+
+Name (PR02, Package() {
+ // [SL02]: PCI Express Slot 2 on 1B on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR02, Package() {
+ // [SL02]: PCI Express Slot 2 on 1B on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH02, Package() {
+ // [SL02]: PCI Express Slot 2 on 1B on PCI0
+ Package() { 0x0000FFFF, 0, 0, 27 },
+ Package() { 0x0000FFFF, 1, 0, 30 },
+ Package() { 0x0000FFFF, 2, 0, 28 },
+ Package() { 0x0000FFFF, 3, 0, 29 },
+})
+
+Name (PR03, Package() {
+ // [CB0I]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [CB0J]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ // [CB0K]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ // [CB0L]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR03, Package() {
+ // [CB0I]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ // [CB0J]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ // [CB0K]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ // [CB0L]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH03, Package() {
+ // [CB0I]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 0, 0, 32 },
+ // [CB0J]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 1, 0, 36 },
+ // [CB0K]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 2, 0, 37 },
+ // [CB0L]: CB3DMA on IOSF
+ Package() { 0x0000FFFF, 3, 0, 38 },
+})
+
+Name (PR04, Package() {
+ // [SL04]: PCI Express Slot 4 on 2B on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR04, Package() {
+ // [SL04]: PCI Express Slot 4 on 2B on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH04, Package() {
+ // [SL04]: PCI Express Slot 4 on 2B on PCI0
+ Package() { 0x0000FFFF, 0, 0, 33 },
+ Package() { 0x0000FFFF, 1, 0, 37 },
+ Package() { 0x0000FFFF, 2, 0, 38 },
+ Package() { 0x0000FFFF, 3, 0, 36 },
+})
+
+Name (PR05, Package() {
+ // [SL05]: PCI Express Slot 5 on 2C on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR05, Package() {
+ // [SL05]: PCI Express Slot 5 on 2C on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH05, Package() {
+ // [SL05]: PCI Express Slot 5 on 2C on PCI0
+ Package() { 0x0000FFFF, 0, 0, 34 },
+ Package() { 0x0000FFFF, 1, 0, 37 },
+ Package() { 0x0000FFFF, 2, 0, 36 },
+ Package() { 0x0000FFFF, 3, 0, 38 },
+})
+
+Name (PR06, Package() {
+ // [SL06]: PCI Express Slot 6 on 2D on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR06, Package() {
+ // [SL06]: PCI Express Slot 6 on 2D on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH06, Package() {
+ // [SL06]: PCI Express Slot 6 on 2D on PCI0
+ Package() { 0x0000FFFF, 0, 0, 35 },
+ Package() { 0x0000FFFF, 1, 0, 36 },
+ Package() { 0x0000FFFF, 2, 0, 38 },
+ Package() { 0x0000FFFF, 3, 0, 37 },
+})
+
+Name (PR07, Package() {
+ // [SL07]: PCI Express Slot 7 on 3A on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR07, Package() {
+ // [SL07]: PCI Express Slot 7 on 3A on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH07, Package() {
+ // [SL07]: PCI Express Slot 7 on 3A on PCI0
+ Package() { 0x0000FFFF, 0, 0, 40 },
+ Package() { 0x0000FFFF, 1, 0, 44 },
+ Package() { 0x0000FFFF, 2, 0, 45 },
+ Package() { 0x0000FFFF, 3, 0, 46 },
+})
+
+Name (PR08, Package() {
+ // [SL08]: PCI Express Slot 8 on 3B on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR08, Package() {
+ // [SL08]: PCI Express Slot 8 on 3B on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH08, Package() {
+ // [SL08]: PCI Express Slot 8 on 3B on PCI0
+ Package() { 0x0000FFFF, 0, 0, 41 },
+ Package() { 0x0000FFFF, 1, 0, 45 },
+ Package() { 0x0000FFFF, 2, 0, 46 },
+ Package() { 0x0000FFFF, 3, 0, 44 },
+})
+
+Name (PR09, Package() {
+ // [SL09]: PCI Express Slot 9 on 3C on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR09, Package() {
+ // [SL09]: PCI Express Slot 9 on 3C on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH09, Package() {
+ // [SL09]: PCI Express Slot 9 on 3C on PCI0
+ Package() { 0x0000FFFF, 0, 0, 42 },
+ Package() { 0x0000FFFF, 1, 0, 45 },
+ Package() { 0x0000FFFF, 2, 0, 44 },
+ Package() { 0x0000FFFF, 3, 0, 46 },
+})
+
+Name (PR0A, Package() {
+ // [SL0A]: PCI Express Slot 10 on 3D on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+})
+
+Name (AR0A, Package() {
+ // [SL0A]: PCI Express Slot 10 on 3D on PCI0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AH0A, Package() {
+ // [SL0A]: PCI Express Slot 10 on 3D on PCI0
+ Package() { 0x0000FFFF, 0, 0, 43 },
+ Package() { 0x0000FFFF, 1, 0, 44 },
+ Package() { 0x0000FFFF, 2, 0, 46 },
+ Package() { 0x0000FFFF, 3, 0, 45 },
+})
+
+
+ // PCI Express Port 1A on PCI0
+Device (BR1A) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR01)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH01)
+ }
+ Return (AR01)
+ }
+
+}
+
+// PCI Express Port 1B on PCI0
+Device (BR1B) {
+ Name (_ADR, 0x00010001)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR02)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH02)
+ }
+ Return (AR02)
+ }
+
+}
+
+// PCI Express Port 2A on PCI0
+Device (BR2A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR03)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH03)
+ }
+ Return (AR03)
+ }
+
+
+ // CB3DMA on IOSF
+ Device (CB0I) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // CB3DMA on IOSF
+ Device (CB0J) {
+ Name (_ADR, 0x00000001)
+ }
+
+ // CB3DMA on IOSF
+ Device (CB0K) {
+ Name (_ADR, 0x00000002)
+ }
+
+ // CB3DMA on IOSF
+ Device (CB0L) {
+ Name (_ADR, 0x00000003)
+ }
+}
+
+// PCI Express Port 2B on PCI0
+Device (BR2B) {
+ Name (_ADR, 0x00020001)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR04)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH04)
+ }
+ Return (AR04)
+ }
+
+}
+
+// PCI Express Port 2C on PCI0
+Device (BR2C) {
+ Name (_ADR, 0x00020002)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR05)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH05)
+ }
+ Return (AR05)
+ }
+
+}
+
+// PCI Express Port 2D on PCI0
+Device (BR2D) {
+ Name (_ADR, 0x00020003)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR06)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH06)
+ }
+ Return (AR06)
+ }
+
+}
+
+// PCI Express Port 3A on PCI0
+Device (BR3A) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR07)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH07)
+ }
+ Return (AR07)
+ }
+
+}
+
+// PCI Express Port 3B on PCI0
+Device (BR3B) {
+ Name (_ADR, 0x00030001)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR08)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH08)
+ }
+ Return (AR08)
+ }
+
+}
+
+// PCI Express Port 3C on PCI0
+Device (BR3C) {
+ Name (_ADR, 0x00030002)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR09)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH09)
+ }
+ Return (AR09)
+ }
+
+}
+
+// PCI Express Port 3D on PCI0
+Device (BR3D) {
+ Name (_ADR, 0x00030003)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR0A)
+ }
+ If (LEqual(APC1, One)) {
+ Return (AH0A)
+ }
+ Return (AR0A)
+ }
+
+}
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl
new file mode 100644
index 0000000000..cefe4f72d5
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn at gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+Name(\APC1, Zero) // IIO IOAPIC
+
+Name(\PICM, Zero) // IOAPIC/8259
+
+Method(_PIC, 1)
+{
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+/* ACPI global NVS */
+//#include "irqlinks.asl"
+
+Scope (\_SB)
+{
+ #include "southcluster.asl"
+
+ #include "pcie1.asl"
+}
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl
new file mode 100644
index 0000000000..d2b0ba9879
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl
@@ -0,0 +1,339 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+Name(_HID,EISAID("PNP0A08")) // PCIe
+Name(_CID,EISAID("PNP0A03")) // PCI
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Name (MCRS, ResourceTemplate() {
+ // Bus Numbers
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00)
+
+ // IO Region 0
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+ // PCI Config Space
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ // IO Region 1
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01)
+
+ // VGA memory (0xa0000-0xbffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000,,, ASEG)
+
+ // OPROM reserved (0xc0000-0xc3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000,,, OPR0)
+
+ // OPROM reserved (0xc4000-0xc7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000,,, OPR1)
+
+ // OPROM reserved (0xc8000-0xcbfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000,,, OPR2)
+
+ // OPROM reserved (0xcc000-0xcffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000,,, OPR3)
+
+ // OPROM reserved (0xd0000-0xd3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000,,, OPR4)
+
+ // OPROM reserved (0xd4000-0xd7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000,,, OPR5)
+
+ // OPROM reserved (0xd8000-0xdbfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000,,, OPR6)
+
+ // OPROM reserved (0xdc000-0xdffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000,,, OPR7)
+
+ // BIOS Extension (0xe0000-0xe3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000,,, ESG0)
+
+ // BIOS Extension (0xe4000-0xe7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000,,, ESG1)
+
+ // BIOS Extension (0xe8000-0xebfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000,,, ESG2)
+
+ // BIOS Extension (0xec000-0xeffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000,,, ESG3)
+
+ // System BIOS (0xf0000-0xfffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000,,, FSEG)
+
+ // PCI Memory Region (Top of memory-0xfeafffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000,
+ 0x6EB00000,,, PMEM)
+
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000,
+ 0x00100000,,, APIC)
+
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000,
+ 0x00100000,,, PCHR)
+
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000380000000000, // Range Minimum
+ 0x0000383FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000004000000000, // Length
+ ,,, AddressRangeMemory, TypeStatic)
+})
+
+Method (_CRS, 0, Serialized) {
+ Return (MCRS)
+}
+
+/* Device Resource Consumption */
+Device (PDRC) {
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, 1)
+
+ Name (PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PSEG_BASE_ADDRESS, PSEG_BASE_SIZE)
+ Memory32Fixed(ReadWrite, IOXAPIC1_BASE_ADDRESS, IOXAPIC1_BASE_SIZE)
+ Memory32Fixed(ReadWrite, IOXAPIC2_BASE_ADDRESS, IOXAPIC2_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PCH_BASE_ADDRESS, PCH_BASE_SIZE)
+ Memory32Fixed(ReadWrite, LXAPIC_BASE_ADDRESS, LXAPIC_BASE_SIZE)
+ Memory32Fixed(ReadWrite, FIRMWARE_BASE_ADDRESS, FIRMWARE_BASE_SIZE)
+ })
+
+ // Current Resource Settings
+ Method (_CRS, 0, Serialized)
+ {
+ Return(PDRS)
+ }
+}
+
+Method (_OSC, 4) {
+ /* Check for proper GUID */
+ If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ }
+ Else
+ {
+ /* Unrecognized UUID */
+ CreateDWordField (Arg3, 0, CDW1)
+ Or (CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+}
+
+Name (PR00, Package() {
+ // [DMI0]: Legacy PCI Express Port 0 on PCI0
+ Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [BR1A]: PCI Express Port 1A on PCI0
+ // [BR1B]: PCI Express Port 1B on PCI0
+ Package() { 0x0001FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [BR2A]: PCI Express Port 2A on PCI0
+ // [BR2B]: PCI Express Port 2B on PCI0
+ // [BR2C]: PCI Express Port 2C on PCI0
+ // [BR2D]: PCI Express Port 2D on PCI0
+ Package() { 0x0002FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [BR3A]: PCI Express Port 3A on PCI0
+ // [BR3B]: PCI Express Port 3B on PCI0
+ // [BR3C]: PCI Express Port 3C on PCI0
+ // [BR3D]: PCI Express Port 3D on PCI0
+ Package() { 0x0003FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [CB0A]: CB3DMA on PCI0
+ // [CB0E]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [CB0B]: CB3DMA on PCI0
+ // [CB0F]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ // [CB0C]: CB3DMA on PCI0
+ // [CB0G]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ // [CB0D]: CB3DMA on PCI0
+ // [CB0H]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+ // [IIM0]: IIOMISC on PCI0
+ Package() { 0x0005FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0005FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0005FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0005FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+ // [IID0]: IIODFX0 on PCI0
+ Package() { 0x0006FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0006FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ Package() { 0x0006FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ Package() { 0x0006FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+ // [XHCI]: xHCI controller 1 on PCH
+ Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+ // [HECI]: ME HECI on PCH
+ // [IDER]: ME IDE redirect on PCH
+ Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [HEC2]: ME HECI2 on PCH
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ // [GBEM]: GbE Controller VPRO
+ Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKE, 0 },
+ // [EHC2]: EHCI controller #2 on PCH
+ Package() { 0x001AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ // [ALZA]: High definition Audio Controller
+ Package() { 0x001BFFFF, 0, \_SB.PCI0.LPC0.LNKG, 0 },
+ // [RP01]: Pci Express Port 1 on PCH
+ // [RP05]: Pci Express Port 5 on PCH
+ Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [RP02]: Pci Express Port 2 on PCH
+ // [RP06]: Pci Express Port 6 on PCH
+ Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
+ // [RP03]: Pci Express Port 3 on PCH
+ // [RP07]: Pci Express Port 7 on PCH
+ Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ // [RP04]: Pci Express Port 4 on PCH
+ // [RP08]: Pci Express Port 8 on ICH
+ Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
+ // [EHC1]: EHCI controller #1 on PCH
+ Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+ // [SAT1]: SATA controller 1 on PCH
+ // [SAT2]: SATA Host controller 2 on PCH
+ Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ // [SMBS]: SMBus controller on PCH
+ // [TERM]: Thermal Subsystem on ICH
+ Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
+})
+
+Name (AR00, Package() {
+ // [DMI0]: Legacy PCI Express Port 0 on PCI0
+ Package() { 0x0000FFFF, 0, 0, 47 },
+ // [BR1A]: PCI Express Port 1A on PCI0
+ // [BR1B]: PCI Express Port 1B on PCI0
+ Package() { 0x0001FFFF, 0, 0, 47 },
+ // [BR2A]: PCI Express Port 2A on PCI0
+ // [BR2B]: PCI Express Port 2B on PCI0
+ // [BR2C]: PCI Express Port 2C on PCI0
+ // [BR2D]: PCI Express Port 2D on PCI0
+ Package() { 0x0002FFFF, 0, 0, 47 },
+ // [BR3A]: PCI Express Port 3A on PCI0
+ // [BR3B]: PCI Express Port 3B on PCI0
+ // [BR3C]: PCI Express Port 3C on PCI0
+ // [BR3D]: PCI Express Port 3D on PCI0
+ Package() { 0x0003FFFF, 0, 0, 47 },
+ // [CB0A]: CB3DMA on PCI0
+ // [CB0E]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 0, 0, 31 },
+ // [CB0B]: CB3DMA on PCI0
+ // [CB0F]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 1, 0, 39 },
+ // [CB0C]: CB3DMA on PCI0
+ // [CB0G]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 2, 0, 31 },
+ // [CB0D]: CB3DMA on PCI0
+ // [CB0H]: CB3DMA on PCI0
+ Package() { 0x0004FFFF, 3, 0, 39 },
+ // [IIM0]: IIOMISC on PCI0
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [IID0]: IIODFX0 on PCI0
+ Package() { 0x0006FFFF, 0, 0, 16 },
+ Package() { 0x0006FFFF, 1, 0, 17 },
+ Package() { 0x0006FFFF, 2, 0, 18 },
+ Package() { 0x0006FFFF, 3, 0, 19 },
+ // [XHCI]: xHCI controller 1 on PCH
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [HECI]: ME HECI on PCH
+ // [IDER]: ME IDE redirect on PCH
+ Package() { 0x0016FFFF, 0, 0, 16 },
+ // [HEC2]: ME HECI2 on PCH
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0016FFFF, 1, 0, 17 },
+ // [GBEM]: GbE Controller VPRO
+ Package() { 0x0019FFFF, 0, 0, 20 },
+ // [EHC2]: EHCI controller #2 on PCH
+ Package() { 0x001AFFFF, 2, 0, 18 },
+ // [ALZA]: High definition Audio Controller
+ Package() { 0x001BFFFF, 0, 0, 22 },
+ // [RP01]: Pci Express Port 1 on PCH
+ // [RP05]: Pci Express Port 5 on PCH
+ Package() { 0x001CFFFF, 0, 0, 16 },
+ // [RP02]: Pci Express Port 2 on PCH
+ // [RP06]: Pci Express Port 6 on PCH
+ Package() { 0x001CFFFF, 1, 0, 17 },
+ // [RP03]: Pci Express Port 3 on PCH
+ // [RP07]: Pci Express Port 7 on PCH
+ Package() { 0x001CFFFF, 2, 0, 18 },
+ // [RP04]: Pci Express Port 4 on PCH
+ // [RP08]: Pci Express Port 8 on ICH
+ Package() { 0x001CFFFF, 3, 0, 19 },
+ // [EHC1]: EHCI controller #1 on PCH
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ // [SAT1]: SATA controller 1 on PCH
+ // [SAT2]: SATA Host controller 2 on PCH
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ // [SMBS]: SMBus controller on PCH
+ // [TERM]: Thermal Subsystem on ICH
+ Package() { 0x001FFFFF, 2, 0, 18 },
+})
+
+// Socket 0 Root bridge
+Method (_PRT, 0) {
+ If (LEqual(PICM, Zero)) {
+ Return (PR00)
+ }
+ Return (AR00) // If you disable the IOxAPIC in IIO, you should return AR00
+}
+
+#include "lpc.asl"
diff --git a/arch/x86/include/asm/arch-broadwell-de/device.h b/arch/x86/include/asm/arch-broadwell-de/device.h
new file mode 100644
index 0000000000..be6df7c018
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/device.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BROADWELL_DE_DEVICE_H_
+#define _BROADWELL_DE_DEVICE_H_
+
+#define BUS0 0
+
+#define SOC_DEV 0
+#define SOC_FUNC 0
+#define SOC_DEVID 0x2F00
+#define SOC_DEVID_ES2 0x6F00
+#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC)
+
+#define VTD_DEV 5
+#define VTD_FUNC 0
+#define VTD_DEVID 0x6f28
+#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC)
+
+#define LPC_DEV 31
+#define LPC_FUNC 0
+#define LPC_DEVID 0x8C42
+#define LPC_DEVID_ES2 0x8C54
+#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC)
+
+#define SATA_DEV 31
+#define SATA_FUNC 2
+#define AHCI_DEVID 0x8C02
+#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC)
+
+#define SMBUS_DEV 31
+#define SMBUS_FUNC 3
+#define SMBUS_DEVID 0x8C22
+#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
+
+#define SATA2_DEV 31
+#define SATA2_FUNC 5
+#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC)
+
+#define EHCI1_DEV 29
+#define EHCI1_FUNC 0
+#define EHCI1_DEVID 0x8C26
+#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1)
+
+#define EHCI2_DEV 26
+#define EHCI2_FUNC 0
+#define EHCI2_DEVID 0x8C2D
+#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2)
+
+#define XHCI_DEV 20
+#define XHCI_FUNC 0
+#define XHCI_DEVID 0x8C31
+#define XHCI_FUS_REG 0xE0
+#define XHCI_FUNC_DISABLE (1 << 0)
+#define XHCI_USB2PR_REG 0xD0
+#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
+
+#define GBE_DEV 25
+#define GBE_FUNC 0
+#define GBE_DEVID 0x8C33
+#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC)
+
+#define ME_DEV 22
+#define ME_FUNC 0
+#define ME_DEVID 0x8C3A
+#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC)
+
+#define HDA_DEV 27
+#define HDA_FUNC 0
+#define HDA_DEVID 0x8C20
+#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC)
+
+#define PCIE_DEV 28
+#define PCIE_PORT1_DEV PCIE_DEV
+#define PCIE_PORT1_FUNC 0
+#define PCIE_PORT1_DEVID 0x8C10
+#define PCIE_PORT2_DEV PCIE_DEV
+#define PCIE_PORT2_FUNC 1
+#define PCIE_PORT2_DEVID 0x8C12
+#define PCIE_PORT3_DEV PCIE_DEV
+#define PCIE_PORT3_FUNC 2
+#define PCIE_PORT3_DEVID 0x8C14
+#define PCIE_PORT4_DEV PCIE_DEV
+#define PCIE_PORT4_FUNC 3
+#define PCIE_PORT4_DEVID 0x8C16
+#define PCIE_PORT5_DEV PCIE_DEV
+#define PCIE_PORT5_FUNC 4
+#define PCIE_PORT5_DEVID 0x8C18
+#define PCIE_PORT6_DEV PCIE_DEV
+#define PCIE_PORT6_FUNC 5
+#define PCIE_PORT6_DEVID 0x8C1A
+#define PCIE_PORT7_DEV PCIE_DEV
+#define PCIE_PORT7_FUNC 6
+#define PCIE_PORT7_DEVID 0x8C1C
+#define PCIE_PORT8_DEV PCIE_DEV
+#define PCIE_PORT8_FUNC 7
+#define PCIE_PORT8_DEVID 0x8C1E
+#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC)
+#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC)
+#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC)
+#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC)
+#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC)
+#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC)
+#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC)
+#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC)
+
+/* The SMM device is located on bus 0xff (QPI) */
+#define QPI_BUS 0xff
+#define SMM_DEV 0x10
+#define SMM_FUNC 0x06
+#define SMM_DEV_FUNC PCI_DEVFN(SMM_DEV, SMM_FUNC)
+
+#endif /* _BROADWELL_DE_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h
new file mode 100644
index 0000000000..139f8b5db4
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#ifndef __ASSEMBLY__
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+#endif
+
+/* FSP user configuration settings */
+
+#define PAM_RW_DMI_ONLY 0
+#define PAM_R_DRAM_W_DMI 1
+#define PAM_R_DMI_W_DRAM 2
+#define PAM_RW_DRAM_ONLY 3
+
+#define PCH_PCI_ASPM_DISABLED 0
+#define PCH_PCI_ASPM_L0S 1
+#define PCH_PCI_ASPM_L1_ONLY 2
+#define PCH_PCI_ASPM_L0SL1 3
+#define PCH_PCI_ASPM_AUTO 4
+
+#define PCIE_ASPM_DISABLED 0
+#define PCIE_ASPM_L1ONLY 2
+#define PCIE_ASPM_AUTO 7
+
+#define MEM_CHANNEL_INTERLEAVE_AUTO 0
+#define MEM_CHANNEL_INTERLEAVE_1WAY 1
+#define MEM_CHANNEL_INTERLEAVE_2WAY 2
+#define MEM_CHANNEL_INTERLEAVE_3WAY 3
+#define MEM_CHANNEL_INTERLEAVE_4WAY 4
+
+#define MEM_SCRAMBLING_DISABLED 0
+#define MEM_SCRAMBLING_ENABLED 1
+#define MEM_SCRAMBLING_AUTO 2
+
+#define MEM_ECC_SUPPORT_DISABLED 0
+#define MEM_ECC_SUPPORT_ENABLED 1
+#define MEM_ECC_SUPPORT_AUTO 2
+
+#define MEM_CA_PARITY_DISABLED 0
+#define MEM_CA_PARITY_ENABLED 1
+#define MEM_CA_PARITY_AUTO 2
+
+#define MEM_POWER_SAVINGS_MODE_DISABLED 0
+#define MEM_POWER_SAVINGS_MODE_SLOW 1
+#define MEM_POWER_SAVINGS_MODE_FAST 2
+#define MEM_POWER_SAVINGS_MODE_APD 3
+#define MEM_POWER_SAVINGS_MODE_USER 4
+#define MEM_POWER_SAVINGS_MODE_AUTO 5
+
+#define MEM_RANK_MARGIN_TOOL_DISABLED 0
+#define MEM_RANK_MARGIN_TOOL_ENABLED 1
+#define MEM_RANK_MARGIN_TOOL_AUTO 2
+
+#define MEM_RANK_MULTIPLICATION_AUTO 0
+#define MEM_RANK_MULTIPLICATION_ENABLED 1
+
+#define MEM_THERMAL_THROTTLING_DISABLED 0
+#define MEM_THERMAL_THROTTLING_OPENLOOP 1
+#define MEM_THERMAL_THROTTLING_CLOSEDLOOP 2
+
+#define MEM_ELECTRICAL_THROTTLING_DISABLED 0
+#define MEM_ELECTRICAL_THROTTLING_ENABLED 1
+#define MEM_ELECTRICAL_THROTTLING_AUTO 2
+
+#define MEM_DDR_MEMORY_TYPE_RDIMM_ONLY 0
+#define MEM_DDR_MEMORY_TYPE_UDIMM_ONLY 1
+#define MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM 2
+
+#define MEM_MC0DT_OVERRIDE_50OHM 0
+#define MEM_MC0DT_OVERRIDE_100OHM 1
+#define MEM_MC0DT_OVERRIDE_AUTO 2
+
+#define MEM_ADR_DISABLED 0
+#define MEM_ADR_ENABLED 1
+#define MEM_ADR_ENABLED_NVDIMM 2
+
+#define MEM_RANK_INTERLEAVE_AUTO 0
+#define MEM_RANK_INTERLEAVE_1WAY 1
+#define MEM_RANK_INTERLEAVE_2WAY 2
+#define MEM_RANK_INTERLEAVE_4WAY 4
+#define MEM_RANK_INTERLEAVE_8WAY 8
+
+#define MEM_PAGE_POLICY_OPEN 0
+#define MEM_PAGE_POLICY_CLOSED 1
+#define MEM_PAGE_POLICY_ADAPTIVE 2
+#define MEM_PAGE_POLICY_AUTO 3
+
+#define MEM_REFRESH_MODE_ACC_SELF_REFRESH 0
+#define MEM_REFRESH_MODE_2X_REFRESH 1
+
+#define MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED 0
+#define MEM_SOCKET_INTERLEAVE_BELOW_4G_ENABLED 1
+
+#define CONFIG_IOU1_PCI_PORT3_X4X4X4X4 0
+#define CONFIG_IOU1_PCI_PORT3_X4X4XXX8 1
+#define CONFIG_IOU1_PCI_PORT3_XXX8X4X4 2
+#define CONFIG_IOU1_PCI_PORT3_XXX8XXX8 3
+#define CONFIG_IOU1_PCI_PORT3_XXXXXX16 4
+
+#define CONFIG_IOU2_PCI_PORT1_X4X4 0
+#define CONFIG_IOU2_PCI_PORT1_XXX8 1
+
+#define SERIAL_PORT_BAUDRATE_9600 8
+#define SERIAL_PORT_BAUDRATE_19200 9
+#define SERIAL_PORT_BAUDRATE_38400 10
+#define SERIAL_PORT_BAUDRATE_57600 11
+#define SERIAL_PORT_BAUDRATE_115200 12
+
+#define SERIAL_PORT_TYPE_NONE 0
+#define SERIAL_PORT_TYPE_IO 1
+#define SERIAL_PORT_TYPE_MMIO 2
+
+#define DEBUG_OUTPUT_LEVEL_DISABLED 0
+#define DEBUG_OUTPUT_LEVEL_MINIMUM 1
+#define DEBUG_OUTPUT_LEVEL_NORMAL 2
+#define DEBUG_OUTPUT_LEVEL_MAXIMUM 3
+
+#define MEM_FAST_BOOT_DISABLE 0
+#define MEM_FAST_BOOT_ENABLE 1
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h
new file mode 100644
index 0000000000..048c528710
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSP_VPD_H
+#define __FSP_VPD_H
+
+struct __packed upd_region {
+ uint64_t signature; /**Offset 0x0000 **/
+ uint64_t reserved; /**Offset 0x0008 **/
+ uint8_t unusedUpdSpace0[16]; /**Offset 0x0010 **/
+ uint8_t serialPortType; /**Offset 0x0020 **/
+ uint32_t serialPortAddress; /**Offset 0x0021 **/
+ uint8_t serialPortConfigure; /**Offset 0x0025 **/
+ uint8_t serialPortBaudRate; /**Offset 0x0026 **/
+ uint8_t serialPortControllerInit0; /**Offset 0x0027 **/
+ uint8_t serialPortControllerInit1; /**Offset 0x0028 **/
+ uint8_t configIOU1_PciPort3; /**Offset 0x0029 **/
+ uint8_t configIOU2_PciPort1; /**Offset 0x002A **/
+ uint8_t powerStateAfterG3; /**Offset 0x002B **/
+ uint8_t pchPciPort1; /**Offset 0x002C **/
+ uint8_t pchPciPort2; /**Offset 0x002D **/
+ uint8_t pchPciPort3; /**Offset 0x002E **/
+ uint8_t pchPciPort4; /**Offset 0x002F **/
+ uint8_t pchPciPort5; /**Offset 0x0030 **/
+ uint8_t pchPciPort6; /**Offset 0x0031 **/
+ uint8_t pchPciPort7; /**Offset 0x0032 **/
+ uint8_t pchPciPort8; /**Offset 0x0033 **/
+ uint8_t hotPlug_PchPciPort1; /**Offset 0x0034 **/
+ uint8_t hotPlug_PchPciPort2; /**Offset 0x0035 **/
+ uint8_t hotPlug_PchPciPort3; /**Offset 0x0036 **/
+ uint8_t hotPlug_PchPciPort4; /**Offset 0x0037 **/
+ uint8_t hotPlug_PchPciPort5; /**Offset 0x0038 **/
+ uint8_t hotPlug_PchPciPort6; /**Offset 0x0039 **/
+ uint8_t hotPlug_PchPciPort7; /**Offset 0x003A **/
+ uint8_t hotPlug_PchPciPort8; /**Offset 0x003B **/
+ uint8_t ehci1Enable; /**Offset 0x003C **/
+ uint8_t ehci2Enable; /**Offset 0x003D **/
+ uint8_t hyperThreading; /**Offset 0x003E **/
+ uint8_t debugOutputLevel; /**Offset 0x003F **/
+ uint8_t tcoTimerHaltLock; /**Offset 0x0040 **/
+ uint8_t turboMode; /**Offset 0x0041 **/
+ uint8_t bootPerfMode; /**Offset 0x0042 **/
+ uint8_t pciePort1aAspm; /**Offset 0x0043 **/
+ uint8_t pciePort1bAspm; /**Offset 0x0044 **/
+ uint8_t pciePort3aAspm; /**Offset 0x0045 **/
+ uint8_t pciePort3bAspm; /**Offset 0x0046 **/
+ uint8_t pciePort3cAspm; /**Offset 0x0047 **/
+ uint8_t pciePort3dAspm; /**Offset 0x0048 **/
+ uint8_t pchPciePort1Aspm; /**Offset 0x0049 **/
+ uint8_t pchPciePort2Aspm; /**Offset 0x004A **/
+ uint8_t pchPciePort3Aspm; /**Offset 0x004B **/
+ uint8_t pchPciePort4Aspm; /**Offset 0x004C **/
+ uint8_t pchPciePort5Aspm; /**Offset 0x004D **/
+ uint8_t pchPciePort6Aspm; /**Offset 0x004E **/
+ uint8_t pchPciePort7Aspm; /**Offset 0x004F **/
+ uint8_t pchPciePort8Aspm; /**Offset 0x0050 **/
+ uint8_t dFXEnable; /**Offset 0x0051 **/
+ uint8_t thermalDeviceEnable; /**Offset 0x0052 **/
+ uint8_t unusedUpdSpace1[88]; /**Offset 0x0053 **/
+ uint8_t memEccSupport; /**Offset 0x00AB **/
+ uint8_t memDdrMemoryType; /**Offset 0x00AC **/
+ uint8_t memRankMultiplication; /**Offset 0x00AD **/
+ uint8_t memRankMarginTool; /**Offset 0x00AE **/
+ uint8_t memScrambling; /**Offset 0x00AF **/
+ uint8_t memRefreshMode; /**Offset 0x00B0 **/
+ uint8_t memMcOdtOverride; /**Offset 0x00B1 **/
+ uint8_t memCAParity; /**Offset 0x00B2 **/
+ uint8_t memThermalThrottling; /**Offset 0x00B3 **/
+ uint8_t memPowerSavingsMode; /**Offset 0x00B4 **/
+ uint8_t memElectricalThrottling; /**Offset 0x00B5 **/
+ uint8_t memPagePolicy; /**Offset 0x00B6 **/
+ uint8_t memSocketInterleaveBelow4G; /**Offset 0x00B7 **/
+ uint8_t memChannelInterleave; /**Offset 0x00B8 **/
+ uint8_t memRankInterleave; /**Offset 0x00B9 **/
+ uint8_t memDownEnable; /**Offset 0x00BA **/
+ uint32_t memDownCh0Dimm0SpdPtr; /**Offset 0x00BB **/
+ uint32_t memDownCh0Dimm1SpdPtr; /**Offset 0x00BF **/
+ uint32_t memDownCh1Dimm0SpdPtr; /**Offset 0x00C3 **/
+ uint32_t memDownCh1Dimm1SpdPtr; /**Offset 0x00C7 **/
+ uint8_t memFastBoot; /**Offset 0x00CB **/
+ uint8_t pam0_hienable; /**Offset 0x00CC **/
+ uint8_t pam1_loenable; /**Offset 0x00CD **/
+ uint8_t pam1_hienable; /**Offset 0x00CE **/
+ uint8_t pam2_loenable; /**Offset 0x00CF **/
+ uint8_t pam2_hienable; /**Offset 0x00D0 **/
+ uint8_t pam3_loenable; /**Offset 0x00D1 **/
+ uint8_t pam3_hienable; /**Offset 0x00D2 **/
+ uint8_t pam4_loenable; /**Offset 0x00D3 **/
+ uint8_t pam4_hienable; /**Offset 0x00D4 **/
+ uint8_t pam5_loenable; /**Offset 0x00D5 **/
+ uint8_t pam5_hienable; /**Offset 0x00D6 **/
+ uint8_t pam6_loenable; /**Offset 0x00D7 **/
+ uint8_t pam6_hienable; /**Offset 0x00D8 **/
+ uint8_t memAdr; /**Offset 0x00D9 **/
+ uint8_t memAdrResumePath; /**Offset 0x00DA **/
+ uint8_t memBlockScTrafficOnAdr; /**Offset 0x00DB **/
+ uint16_t memPlatformReleaseAdrClampsPort;/**Offset 0x00DC **/
+ uint32_t memPlatformReleaseAdrClampsAnd; /**Offset 0x00DE **/
+ uint32_t memPlatformReleaseAdrClampsOr; /**Offset 0x00E2 **/
+ uint8_t unusedUpdSpace2[24]; /**Offset 0x00E6 **/
+ uint16_t terminator; /**Offset 0x00FE **/
+};
+
+#define VPD_IMAGE_ID 0x5F45442D5844425F /* '_BDX-DE_' */
+
+struct __packed vpd_region {
+ uint64_t sign; /* Offset 0x0000 */
+ uint32_t img_rev; /* Offset 0x0008 */
+ uint32_t upd_offset; /* Offset 0x000c */
+ uint8_t unused[16]; /* Offset 0x0010 */
+ uint32_t fsp_res_memlen; /* Offset 0x0020 */
+};
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell-de/global_nvs.h b/arch/x86/include/asm/arch-broadwell-de/global_nvs.h
new file mode 100644
index 0000000000..5097cc1282
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/global_nvs.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn at gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BROADWELL_DE_GLOBAL_NVS_H_
+#define _BROADWELL_DE_GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+ u8 pcnt; /* processor count */
+ u8 iuart_en; /* internal UART enabled */
+
+ /*
+ * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+ * This must match the size defined in the global_nvs.asl.
+ */
+ u8 rsvd[254];
+};
+
+#endif /* _BROADWELL_DE_GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/arch-broadwell-de/iomap.h b/arch/x86/include/asm/arch-broadwell-de/iomap.h
new file mode 100644
index 0000000000..80f2b9d937
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/iomap.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BROADWELL_DE_IOMAP_H_
+#define _BROADWELL_DE_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE //CONFIG_MMCONF_BASE_ADDRESS in Coreboot
+#define MCFG_BASE_SIZE 0x10000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS 0xfeb00000
+#define ABORT_BASE_SIZE 0x00010000
+
+/* PSEG */
+#define PSEG_BASE_ADDRESS 0xfeb80000
+#define PSEG_BASE_SIZE 0x00080000
+
+/* IOxAPIC */
+#define IOXAPIC1_BASE_ADDRESS 0xfec00000
+#define IOXAPIC1_BASE_SIZE 0x00100000
+#define IOXAPIC2_BASE_ADDRESS 0xfec01000
+#define IOXAPIC2_BASE_SIZE 0x00100000
+
+/* PCH (HPET/LT/TPM/Others) */
+#define PCH_BASE_ADDRESS 0xfed00000
+#define PCH_BASE_SIZE 0x00100000
+
+/* Local XAPIC */
+#define LXAPIC_BASE_ADDRESS 0xfee00000
+#define LXAPIC_BASE_SIZE 0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* Firmware */
+#define FIRMWARE_BASE_ADDRESS 0xff000000
+#define FIRMWARE_BASE_SIZE 0x01000000
+
+/*
+ * IO Port bases.
+ */
+
+/* ACPI Base Address */
+#define ACPI_BASE_ADDRESS 0x400
+#define ACPI_BASE_SIZE 0x80
+
+/* GPIO Base Address */
+#define GPIO_BASE_ADDRESS 0x500
+#define GPIO_BASE_SIZE 0x80
+
+#endif /* _BROADWELL_DE_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-broadwell-de/irq.h b/arch/x86/include/asm/arch-broadwell-de/irq.h
new file mode 100644
index 0000000000..ac6f689479
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/irq.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove at prodrive-technologies.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BROADWELL_DE_IRQ_H_
+#define _BROADWELL_DE_IRQ_H_
+
+#define PIRQA_APIC_IRQ 16
+#define PIRQB_APIC_IRQ 17
+#define PIRQC_APIC_IRQ 18
+#define PIRQD_APIC_IRQ 19
+#define PIRQE_APIC_IRQ 20
+#define PIRQF_APIC_IRQ 21
+#define PIRQG_APIC_IRQ 22
+#define PIRQH_APIC_IRQ 23
+
+/* PIC IRQ settings. */
+#define PIRQ_PIC_IRQ3 0x3
+#define PIRQ_PIC_IRQ4 0x4
+#define PIRQ_PIC_IRQ5 0x5
+#define PIRQ_PIC_IRQ6 0x6
+#define PIRQ_PIC_IRQ7 0x7
+#define PIRQ_PIC_IRQ9 0x9
+#define PIRQ_PIC_IRQ10 0xa
+#define PIRQ_PIC_IRQ11 0xb
+#define PIRQ_PIC_IRQ12 0xc
+#define PIRQ_PIC_IRQ14 0xe
+#define PIRQ_PIC_IRQ15 0xf
+#define PIRQ_PIC_IRQDISABLE 0x80
+#define PIRQ_PIC_UNKNOWN_UNUSED 0xff
+
+/* Overloaded term, but these values determine the per device route. */
+#define PIRQA 0
+#define PIRQB 1
+#define PIRQC 2
+#define PIRQD 3
+#define PIRQE 4
+#define PIRQF 5
+#define PIRQG 6
+#define PIRQH 7
+
+#define ACPI_CNTL_OFFSET 0x44
+#define SCIS_MASK 0x07
+#define SCIS_IRQ9 0x00
+#define SCIS_IRQ10 0x01
+#define SCIS_IRQ11 0x02
+#define SCIS_IRQ20 0x04
+#define SCIS_IRQ21 0x05
+#define SCIS_IRQ22 0x06
+#define SCIS_IRQ23 0x07
+
+/* In each mainboard directory there should exist a header file irqroute.h that
+ * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
+ * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */
+
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
+#include <stdint.h>
+
+#define NUM_OF_PCI_DEVS 32
+#define NUM_PIRQS 8
+
+struct broadwell_de_irq_route {
+ /* Per device configuration. */
+ uint16_t pcidev[NUM_OF_PCI_DEVS];
+ /* Route path for each internal PIRQx in PIC mode. */
+ uint8_t pic[NUM_PIRQS];
+};
+
+extern const struct broadwell_de_irq_route global_broadwell_de_irq_route;
+
+#define DEFINE_IRQ_ROUTES \
+ const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \
+ .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \
+ .pic = { PIRQ_PIC_ROUTES, }, \
+ }
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+ [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
+ ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)
+
+#define PIRQ_PIC(pirq_, pic_irq_) \
+ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
+
+#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
+
+#endif /* _BROADWELL_DE_IRQ_H_ */
--
2.11.0
More information about the U-Boot
mailing list