[U-Boot] [PATCH v3 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb
Calvin Johnson
calvin.johnson at nxp.com
Sat Mar 3 17:43:38 UTC 2018
This patch enables ethernet support for ls1012ardb.
Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>
Acked-by: Joe Hershberger <joe.hershberger at ni.com>
---
Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
board/freescale/ls1012ardb/Kconfig | 29 +++++++++
board/freescale/ls1012ardb/Makefile | 1 +
board/freescale/ls1012ardb/eth.c | 106 ++++++++++++++++++++++++++++++++
board/freescale/ls1012ardb/ls1012ardb.c | 4 --
include/configs/ls1012ardb.h | 4 ++
5 files changed, 140 insertions(+), 4 deletions(-)
create mode 100644 board/freescale/ls1012ardb/eth.c
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index d13b08e..af35a01 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,6 +12,35 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012ardb"
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select PHYLIB
+ imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x1
+
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
index 05fa9d9..bd80ce5 100644
--- a/board/freescale/ls1012ardb/Makefile
+++ b/board/freescale/ls1012ardb/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1012ardb.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
new file mode 100644
index 0000000..e6379a3
--- /dev/null
+++ b/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <i2c.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+ /* Through reset IO expander reset both RGMII and SGMII PHYs */
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+ mdelay(10);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+ mdelay(10);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+ mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+ static int init_done;
+ struct mii_dev *bus;
+ struct pfe_mdio_info mac_mdio_info;
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ if (!init_done) {
+ ls1012ardb_reset_phy();
+ mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ init_done = 1;
+ }
+
+ pfe_set_mdio(priv->gemac_port,
+ miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+ if (!priv->gemac_port) {
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ } else {
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_RGMII_TXID);
+ }
+ return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ .phy_interface = 0,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+ .phy_interface = 1,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata1,
+};
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index c9557bb..ed5a8e6 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -114,10 +114,6 @@ int dram_init(void)
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
int board_early_init_f(void)
{
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 97ed909..43f6236 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -25,6 +25,7 @@
*/
#define I2C_MUX_IO_ADDR 0x24
+#define I2C_MUX_IO2_ADDR 0x25
#define I2C_MUX_IO_0 0
#define I2C_MUX_IO_1 1
#define SW_BOOT_MASK 0x03
@@ -39,6 +40,9 @@
#define SW_REV_C2 0xD8
#define SW_REV_D 0xD0
#define SW_REV_E 0xC8
+#define __PHY_MASK 0xF9
+#define __PHY_ETH2_MASK 0xFB
+#define __PHY_ETH1_MASK 0xFD
/* MMC */
#ifdef CONFIG_MMC
--
2.7.4
More information about the U-Boot
mailing list