[U-Boot] [PATCH 2/3] fpgamap/misc: Add ihs_fpga and gdsys_soc drivers

Mario Six mario.six at gdsys.cc
Wed Mar 28 12:37:29 UTC 2018


This patch adds drivers for IHS FPGAs and their associated busses.

Signed-off-by: Mario Six <mario.six at gdsys.cc>
---
 drivers/fpgamap/Kconfig       |  11 +
 drivers/fpgamap/Makefile      |   1 +
 drivers/fpgamap/ihs_fpgamap.c | 811 ++++++++++++++++++++++++++++++++++++++++++
 drivers/misc/Kconfig          |  10 +
 drivers/misc/Makefile         |   2 +
 drivers/misc/gdsys_soc.c      |  67 ++++
 drivers/misc/gdsys_soc.h      |  24 ++
 7 files changed, 926 insertions(+)
 create mode 100644 drivers/fpgamap/ihs_fpgamap.c
 create mode 100644 drivers/misc/gdsys_soc.c
 create mode 100644 drivers/misc/gdsys_soc.h

diff --git a/drivers/fpgamap/Kconfig b/drivers/fpgamap/Kconfig
index b57d31e3f7..d32043ebfd 100644
--- a/drivers/fpgamap/Kconfig
+++ b/drivers/fpgamap/Kconfig
@@ -7,3 +7,14 @@ menuconfig FPGAMAP
 	  Generic read/write operations with varying widths (8, 16, and 32 for
 	  now), as well as read/write access to named registers (defined via
 	  device tree entries) are supported
+
+if FPGAMAP
+
+config IHS_FPGAMAP
+	bool "Enable IHS FPGA register map driver"
+	depends on DM
+	help
+	  Support for IHS FPGA register map on a gdsys IHS FPGA used on gdsys
+	  boards.
+
+endif
diff --git a/drivers/fpgamap/Makefile b/drivers/fpgamap/Makefile
index c32efba771..80153b34a0 100644
--- a/drivers/fpgamap/Makefile
+++ b/drivers/fpgamap/Makefile
@@ -6,3 +6,4 @@
 #

 obj-$(CONFIG_FPGAMAP) += fpgamap-uclass.o
+obj-$(CONFIG_IHS_FPGAMAP) += ihs_fpgamap.o
diff --git a/drivers/fpgamap/ihs_fpgamap.c b/drivers/fpgamap/ihs_fpgamap.c
new file mode 100644
index 0000000000..7cac696e5b
--- /dev/null
+++ b/drivers/fpgamap/ihs_fpgamap.c
@@ -0,0 +1,811 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario.six at gdsys.cc
+ *
+ * based on the ioep-fpga driver, which is
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <fpgamap.h>
+#include <misc.h>
+#include <mapmem.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct reg_spec {
+	uint addr;
+	uint shift;
+	ulong mask;
+};
+
+struct ihs_fpga_priv {
+	u8 *regs;
+	fdt_addr_t addr;
+	struct gpio_desc reset_gpio;
+	struct gpio_desc done_gpio;
+	struct gpio_desc startupfin_gpios[2];
+	ofnode regmap_node;
+	bool has_osd;
+};
+
+const u16 reflection_testpattern = 0xdede;
+
+enum pcb_video_type {
+	PCB_DVI_SL,
+	PCB_DP_165MPIX,
+	PCB_DP_300MPIX,
+	PCB_HDMI,
+	PCB_DP_1_2,
+	PCB_HDMI_2_0,
+};
+
+enum pcb_transmission_type {
+	PCB_CAT_1G,
+	PCB_FIBER_3G,
+	PCB_CAT_10G,
+	PCB_FIBER_10G,
+};
+
+enum carrier_speed {
+	CARRIER_SPEED_1G,
+	CARRIER_SPEED_3G,
+	CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
+	CARRIER_SPEED_10G,
+};
+
+enum ram_config {
+	RAM_DDR2_32BIT_295MBPS,
+	RAM_DDR3_32BIT_590MBPS,
+	RAM_DDR3_48BIT_590MBPS,
+	RAM_DDR3_64BIT_1800MBPS,
+	RAM_DDR3_48BIT_1800MBPS,
+};
+
+enum sysclock {
+	SYSCLK_147456,
+};
+
+struct fpga_versions {
+	bool video_channel;
+	bool con_side;
+	enum pcb_video_type pcb_video_type;
+	enum pcb_transmission_type pcb_transmission_type;
+	unsigned int hw_version;
+};
+
+struct fpga_features {
+	u8 video_channels;
+	u8 carriers;
+	enum carrier_speed carrier_speed;
+	enum ram_config ram_config;
+	enum sysclock sysclock;
+
+	bool pcm_tx;
+	bool pcm_rx;
+	bool spdif_tx;
+	bool spdif_rx;
+	bool usb2;
+	bool rs232;
+	bool compression_type1;
+	bool compression_type2;
+	bool compression_type3;
+	bool interlace;
+	bool osd;
+	bool compression_pipes;
+};
+
+#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
+
+static int get_versions(struct udevice *dev, struct fpga_versions *versions)
+{
+	enum {
+		VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
+		VERSIONS_FPGA_CON_SIDE = BIT(13),
+		VERSIONS_FPGA_SC = BIT(14),
+		VERSIONS_PCB_CON = BIT(9),
+		VERSIONS_PCB_SC = BIT(8),
+		VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
+		VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
+		VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
+		VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
+		VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
+		VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
+		VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
+		VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
+		VERSIONS_HW_VER_MASK = 0xf << 0,
+	};
+	uint raw_versions;
+
+	memset(versions, 0, sizeof(struct fpga_versions));
+
+	fpgamap_get_reg(dev, "versions", &raw_versions);
+
+	versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
+	versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
+
+	switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
+	case VERSIONS_PCB_VIDEO_DP_1_2:
+		versions->pcb_video_type = PCB_DP_1_2;
+		break;
+
+	case VERSIONS_PCB_VIDEO_HDMI_2_0:
+		versions->pcb_video_type = PCB_HDMI_2_0;
+		break;
+	}
+
+	switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
+	case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
+		versions->pcb_transmission_type = PCB_FIBER_10G;
+		break;
+
+	case VERSIONS_PCB_TRANSMISSION_CAT_10G:
+		versions->pcb_transmission_type = PCB_CAT_10G;
+		break;
+
+	case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
+		versions->pcb_transmission_type = PCB_FIBER_3G;
+		break;
+
+	case VERSIONS_PCB_TRANSMISSION_CAT_1G:
+		versions->pcb_transmission_type = PCB_CAT_1G;
+		break;
+	}
+
+	versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+	return 0;
+}
+
+static int get_features(struct udevice *dev, struct fpga_features *features)
+{
+	enum {
+		FEATURE_SPDIF_RX = BIT(15),
+		FEATURE_SPDIF_TX = BIT(14),
+		FEATURE_PCM_RX = BIT(13),
+		FEATURE_PCM_TX = BIT(12),
+		FEATURE_RAM_MASK = GENMASK(11, 8),
+		FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
+		FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
+		FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
+		FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
+		FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
+		FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
+		FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
+		FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
+		FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
+		FEATURE_CARRIERS_MASK = GENMASK(5, 4),
+		FEATURE_CARRIERS_0 = 0x0 << 4,
+		FEATURE_CARRIERS_1 = 0x1 << 4,
+		FEATURE_CARRIERS_2 = 0x2 << 4,
+		FEATURE_CARRIERS_4 = 0x3 << 4,
+		FEATURE_USB2 = BIT(3),
+		FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
+		FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
+		FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
+		FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
+		FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
+	};
+
+	enum {
+		EXT_FEATURE_OSD = BIT(15),
+		EXT_FEATURE_ETHERNET = BIT(9),
+		EXT_FEATURE_INTERLACE = BIT(8),
+		EXT_FEATURE_RS232 = BIT(7),
+		EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
+		EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
+		EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
+		EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
+		EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
+		EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
+		EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
+	};
+
+	uint raw_features;
+	uint raw_extended_features;
+
+	memset(features, 0, sizeof(struct fpga_features));
+
+	fpgamap_get_reg(dev, "fpga-features", &raw_features);
+	fpgamap_get_reg(dev, "fpga-ext-features", &raw_extended_features);
+
+	switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
+	case FEATURE_VIDEOCHANNELS_0:
+		features->video_channels = 0;
+		break;
+
+	case FEATURE_VIDEOCHANNELS_1:
+		features->video_channels = 1;
+		break;
+
+	case FEATURE_VIDEOCHANNELS_1_1:
+	case FEATURE_VIDEOCHANNELS_2:
+		features->video_channels = 2;
+		break;
+	};
+
+	switch (raw_features & FEATURE_CARRIERS_MASK) {
+	case FEATURE_CARRIERS_0:
+		features->carriers = 0;
+		break;
+
+	case FEATURE_CARRIERS_1:
+		features->carriers = 1;
+		break;
+
+	case FEATURE_CARRIERS_2:
+		features->carriers = 2;
+		break;
+
+	case FEATURE_CARRIERS_4:
+		features->carriers = 4;
+		break;
+	}
+
+	switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
+	case FEATURE_CARRIER_SPEED_1G:
+		features->carrier_speed = CARRIER_SPEED_1G;
+		break;
+	case FEATURE_CARRIER_SPEED_2_5G:
+		features->carrier_speed = CARRIER_SPEED_2_5G;
+		break;
+	case FEATURE_CARRIER_SPEED_10G:
+		features->carrier_speed = CARRIER_SPEED_10G;
+		break;
+	}
+
+	switch (raw_features & FEATURE_RAM_MASK) {
+	case FEATURE_RAM_DDR2_32BIT_295MBPS:
+		features->ram_config = RAM_DDR2_32BIT_295MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_32BIT_590MBPS:
+		features->ram_config = RAM_DDR3_32BIT_590MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_48BIT_590MBPS:
+		features->ram_config = RAM_DDR3_48BIT_590MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_64BIT_1800MBPS:
+		features->ram_config = RAM_DDR3_64BIT_1800MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_48BIT_1800MBPS:
+		features->ram_config = RAM_DDR3_48BIT_1800MBPS;
+		break;
+	}
+
+	features->pcm_tx = raw_features & FEATURE_PCM_TX;
+	features->pcm_rx = raw_features & FEATURE_PCM_RX;
+	features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
+	features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
+	features->usb2 = raw_features & FEATURE_USB2;
+	features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
+	features->compression_type1 = raw_extended_features &
+					EXT_FEATURE_COMPRESSION_TYPE1;
+	features->compression_type2 = raw_extended_features &
+					EXT_FEATURE_COMPRESSION_TYPE2;
+	features->compression_type3 = raw_extended_features &
+					EXT_FEATURE_COMPRESSION_TYPE3;
+	features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
+	features->osd = raw_extended_features & EXT_FEATURE_OSD;
+	features->compression_pipes = raw_extended_features &
+					EXT_FEATURE_COMPRESSION_PERF_MASK;
+
+	return 0;
+}
+
+#else
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
+{
+	enum {
+		/* HW version encoding is a mess, leave it for the moment */
+		VERSIONS_HW_VER_MASK = 0xf << 0,
+		VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
+		VERSIONS_SFP = BIT(5),
+		VERSIONS_VIDEO_MASK = 0x7 << 6,
+		VERSIONS_VIDEO_DVI = 0x0 << 6,
+		VERSIONS_VIDEO_DP_165 = 0x1 << 6,
+		VERSIONS_VIDEO_DP_300 = 0x2 << 6,
+		VERSIONS_VIDEO_HDMI = 0x3 << 6,
+		VERSIONS_UT_MASK = 0xf << 12,
+		VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
+		VERSIONS_UT_MAIN_USER = 0x1 << 12,
+		VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
+		VERSIONS_UT_VIDEO_USER = 0x3 << 12,
+	};
+	u16 raw_versions;
+
+	memset(versions, 0, sizeof(struct fpga_versions));
+
+	FPGA_GET_REG(fpga, versions, &raw_versions);
+
+	switch (raw_versions & VERSIONS_UT_MASK) {
+	case VERSIONS_UT_MAIN_SERVER:
+		versions->video_channel = false;
+		versions->con_side = false;
+		break;
+
+	case VERSIONS_UT_MAIN_USER:
+		versions->video_channel = false;
+		versions->con_side = true;
+		break;
+
+	case VERSIONS_UT_VIDEO_SERVER:
+		versions->video_channel = true;
+		versions->con_side = false;
+		break;
+
+	case VERSIONS_UT_VIDEO_USER:
+		versions->video_channel = true;
+		versions->con_side = true;
+		break;
+	}
+
+	switch (raw_versions & VERSIONS_VIDEO_MASK) {
+	case VERSIONS_VIDEO_DVI:
+		versions->pcb_video_type = PCB_DVI_SL;
+		break;
+
+	case VERSIONS_VIDEO_DP_165:
+		versions->pcb_video_type = PCB_DP_165MPIX;
+		break;
+
+	case VERSIONS_VIDEO_DP_300:
+		versions->pcb_video_type = PCB_DP_300MPIX;
+		break;
+
+	case VERSIONS_VIDEO_HDMI:
+		versions->pcb_video_type = PCB_HDMI;
+		break;
+	}
+
+	versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+	if (raw_versions & VERSIONS_SFP)
+		versions->pcb_transmission_type = PCB_FIBER_3G;
+	else
+		versions->pcb_transmission_type = PCB_CAT_1G;
+
+	return 0;
+}
+
+static int get_features(unsigned int fpga, struct fpga_features *features)
+{
+	enum {
+		FEATURE_CARRIER_SPEED_2_5 = BIT(4),
+		FEATURE_RAM_MASK = 0x7 << 5,
+		FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
+		FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
+		FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
+		FEATURE_PCM_AUDIO_TX = BIT(9),
+		FEATURE_PCM_AUDIO_RX = BIT(10),
+		FEATURE_OSD = BIT(11),
+		FEATURE_USB20 = BIT(12),
+		FEATURE_COMPRESSION_MASK = 7 << 13,
+		FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
+		FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
+		FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
+	};
+
+	enum {
+		EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
+		EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
+		EXTENDED_FEATURE_RS232 = BIT(2),
+		EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
+		EXTENDED_FEATURE_INTERLACE = BIT(4),
+	};
+
+	u16 raw_features;
+	u16 raw_extended_features;
+
+	memset(features, 0, sizeof(struct fpga_features));
+
+	FPGA_GET_REG(fpga, fpga_features, &raw_features);
+	FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+
+	features->video_channels = raw_features & 0x3;
+	features->carriers = (raw_features >> 2) & 0x3;
+
+	features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
+		? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
+
+	switch (raw_features & FEATURE_RAM_MASK) {
+	case FEATURE_RAM_DDR2_32BIT:
+		features->ram_config = RAM_DDR2_32BIT_295MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_32BIT:
+		features->ram_config = RAM_DDR3_32BIT_590MBPS;
+		break;
+
+	case FEATURE_RAM_DDR3_48BIT:
+		features->ram_config = RAM_DDR3_48BIT_590MBPS;
+		break;
+	}
+
+	features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
+	features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
+	features->spdif_tx = raw_extended_features &
+				EXTENDED_FEATURE_SPDIF_AUDIO_TX;
+	features->spdif_rx = raw_extended_features &
+				EXTENDED_FEATURE_SPDIF_AUDIO_RX;
+
+	features->usb2 = raw_features & FEATURE_USB20;
+	features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
+
+	features->compression_type1 = false;
+	features->compression_type2 = false;
+	features->compression_type3 = false;
+	switch (raw_features & FEATURE_COMPRESSION_MASK) {
+	case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
+		features->compression_type3 = true;
+	case FEATURE_COMPRESSION_TYPE1_TYPE2:
+		features->compression_type2 = true;
+	case FEATURE_COMPRESSION_TYPE1:
+		features->compression_type1 = true;
+		break;
+	}
+
+	features->interlace = raw_extended_features &
+				EXTENDED_FEATURE_INTERLACE;
+	features->osd = raw_features & FEATURE_OSD;
+	features->compression_pipes = raw_extended_features &
+					EXTENDED_FEATURE_COMPRESSION_PIPES;
+
+	return 0;
+}
+
+#endif
+
+static void fpga_print_info(struct udevice *dev)
+{
+	struct ihs_fpga_priv *priv = dev_get_priv(dev);
+	uint fpga_version;
+	struct fpga_versions versions;
+	struct fpga_features features;
+
+	fpgamap_get_reg(dev, "fpga-version", &fpga_version);
+	get_versions(dev, &versions);
+	get_features(dev, &features);
+
+	priv->has_osd = features.osd;
+
+	if (versions.video_channel)
+		printf("Videochannel");
+	else
+		printf("Mainchannel");
+
+	if (versions.con_side)
+		printf(" User");
+	else
+		printf(" Server");
+
+// FIXME
+#if 0
+		if (versions & (1<<4))
+			printf(" UC");
+#endif
+
+	switch (versions.pcb_transmission_type) {
+	case PCB_CAT_1G:
+	case PCB_CAT_10G:
+		printf(" CAT");
+		break;
+	case PCB_FIBER_3G:
+	case PCB_FIBER_10G:
+		printf(" Fiber");
+		break;
+	};
+
+	switch (versions.pcb_video_type) {
+	case PCB_DVI_SL:
+		printf(" DVI,");
+		break;
+	case PCB_DP_165MPIX:
+		printf(" DP 165MPix/s,");
+		break;
+	case PCB_DP_300MPIX:
+		printf(" DP 300MPix/s,");
+		break;
+	case PCB_HDMI:
+		printf(" HDMI,");
+		break;
+	case PCB_DP_1_2:
+		printf(" DP 1.2,");
+		break;
+	case PCB_HDMI_2_0:
+		printf(" HDMI 2.0,");
+		break;
+	}
+
+	printf(" FPGA V %d.%02d\n       features: ",
+	       fpga_version / 100, fpga_version % 100);
+
+	if (!features.compression_type1 &&
+	    !features.compression_type2 &&
+	    !features.compression_type3)
+		printf("no compression, ");
+
+	if (features.compression_type1)
+		printf("type1, ");
+
+	if (features.compression_type2)
+		printf("type2, ");
+
+	if (features.compression_type3)
+		printf("type3, ");
+
+	printf("%sosd", features.osd ? "" : "no ");
+
+	if (features.pcm_rx && features.pcm_tx)
+		printf(", pcm rx+tx");
+	else if (features.pcm_rx)
+		printf(", pcm rx");
+	else if (features.pcm_tx)
+		printf(", pcm tx");
+
+	if (features.spdif_rx && features.spdif_tx)
+		printf(", spdif rx+tx");
+	else if (features.spdif_rx)
+		printf(", spdif rx");
+	else if (features.spdif_tx)
+		printf(", spdif tx");
+
+	puts(",\n       ");
+
+	switch (features.sysclock) {
+	case SYSCLK_147456:
+		printf("clock 147.456 MHz");
+		break;
+	}
+
+	switch (features.ram_config) {
+	case RAM_DDR2_32BIT_295MBPS:
+		printf(", RAM 32 bit DDR2");
+		break;
+	case RAM_DDR3_32BIT_590MBPS:
+		printf(", RAM 32 bit DDR3");
+		break;
+	case RAM_DDR3_48BIT_590MBPS:
+	case RAM_DDR3_48BIT_1800MBPS:
+		printf(", RAM 48 bit DDR3");
+		break;
+	case RAM_DDR3_64BIT_1800MBPS:
+		printf(", RAM 64 bit DDR3");
+		break;
+	}
+
+	printf(", %d carrier(s)", features.carriers);
+
+	switch (features.carrier_speed) {
+	case CARRIER_SPEED_1G:
+		printf(", 1Gbit/s");
+		break;
+	case CARRIER_SPEED_3G:
+		printf(", 3Gbit/s");
+		break;
+	case CARRIER_SPEED_10G:
+		printf(", 10Gbit/s");
+		break;
+	}
+
+	printf(", %d video channel(s)\n", features.video_channels);
+}
+
+static int do_reflection_test(struct udevice *dev)
+{
+	int ctr = 0;
+
+	while (1) {
+		uint val;
+
+		fpgamap_set_reg(dev, "reflection-low", reflection_testpattern);
+
+		fpgamap_get_reg(dev, "reflection-low", &val);
+		if (val == (~reflection_testpattern & 0xffff))
+			return 1;
+
+		mdelay(100);
+		if (ctr++ > 5)
+			return 0;
+	}
+}
+
+static int get_reg_spec(struct udevice *dev, const char *compat,
+			struct reg_spec *spec)
+{
+	struct ihs_fpga_priv *priv = dev_get_priv(dev);
+	ofnode subnode;
+
+	for (subnode = ofnode_first_subnode(priv->regmap_node);
+	     ofnode_valid(subnode);
+	     subnode = ofnode_next_subnode(subnode)) {
+		const char *compatprop;
+		u32 reg[3];
+		uint start_bit, end_bit;
+
+		compatprop = ofnode_get_property(subnode, "compatible", NULL);
+
+		if (!strcmp(compatprop, compat)) {
+			ofnode_read_u32_array(subnode, "reg", reg, 3);
+
+			start_bit = reg[1];
+			end_bit = reg[1] - reg[2] + 1;
+
+			spec->mask = GENMASK(start_bit, end_bit);
+			spec->addr = reg[0];
+			spec->shift = end_bit;
+
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static int ihs_fpga_set_reg(struct udevice *dev, const char *compat,
+			    uint value)
+{
+	struct ihs_fpga_priv *priv = dev_get_priv(dev);
+	struct reg_spec spec;
+
+	if (get_reg_spec(dev, compat, &spec)) {
+		printf("%s: Could not get %s regspec for '%s'.\n", __func__,
+		       dev->name, compat);
+		return -ENODEV;
+	}
+
+	out_le16((void *)(priv->regs + spec.addr), value << spec.shift);
+
+	return 0;
+}
+
+static int ihs_fpga_get_reg(struct udevice *dev, const char *compat,
+			    uint *value)
+{
+	struct ihs_fpga_priv *priv = dev_get_priv(dev);
+	struct reg_spec spec;
+	uint tmp;
+
+	if (get_reg_spec(dev, compat, &spec)) {
+		printf("%s: Could not get %s regspec for '%s'.\n", __func__,
+		       dev->name, compat);
+		return -ENODEV;
+	}
+
+	tmp = in_le16((void *)(priv->regs + spec.addr));
+	*value = (tmp & spec.mask) >> spec.shift;
+
+	return 0;
+}
+
+static int ihs_fpga_read(struct udevice *dev, ulong address, void *data,
+			 enum fpgamap_size_t size)
+{
+	struct ihs_fpga_priv *priv = dev_get_priv(dev);
+	u16 *d = data;
+
+	/* TODO: MCLink transfer */
+
+	if (size != FPGAMAP_SIZE_16)
+		return -ENODEV;
+
+	*d = in_le16((void *)(priv->regs + address));
+
+	return 0;
+}
+
+static int ihs_fpga_write(struct udevice *dev, ulong address, void *data,
+			    enum fpgamap_size_t size)
+{
+	struct ihs_fpga_priv *priv = dev_get_priv(dev);
+	u16 *d = data;
+
+	if (size != FPGAMAP_SIZE_16)
+		return -ENODEV;
+
+	/* TODO: MCLink transfer */
+
+	out_le16((void *)(priv->regs + address), *d);
+
+	return 0;
+}
+
+static const struct fpgamap_ops ihs_fpga_ops = {
+	.set_reg = ihs_fpga_set_reg,
+	.get_reg = ihs_fpga_get_reg,
+	.read = ihs_fpga_read,
+	.write = ihs_fpga_write,
+};
+
+static int ihs_fpga_probe(struct udevice *dev)
+{
+	struct ihs_fpga_priv *priv = dev_get_priv(dev);
+	struct ofnode_phandle_args args;
+	u32 reg[3];
+	u32 addr;
+
+	if (dev_read_phandle_with_args(dev, "regmap", NULL, 0, 0, &args)) {
+		printf("%s: Could not get regmap.\n", dev->name);
+		return 1;
+	}
+
+	priv->regmap_node = args.node;
+
+	/* TODO: FPGA attached to MCLink bus */
+
+	dev_read_u32_array(dev, "reg", reg, 3);
+	addr = dev_translate_address(dev, reg);
+	priv->regs = map_sysmem(addr, reg[2]);
+
+	gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
+			     GPIOD_IS_OUT);
+	if (!priv->reset_gpio.dev) {
+		printf("%s: Could not get reset-GPIO.\n", dev->name);
+		return 1;
+	}
+
+	gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio,
+			     GPIOD_IS_IN);
+	if (!priv->done_gpio.dev) {
+		printf("%s: Could not get done-GPIO.\n", dev->name);
+		return 1;
+	}
+
+	dm_gpio_set_value(&priv->reset_gpio, 1);
+
+	if (!do_reflection_test(dev)) {
+		int ctr = 0;
+
+		dm_gpio_set_value(&priv->reset_gpio, 0);
+
+		while (!dm_gpio_get_value(&priv->done_gpio)) {
+			mdelay(100);
+			if (ctr++ > 5) {
+				printf("Initializing FPGA failed\n");
+				break;
+			}
+		}
+
+		udelay(10);
+
+		dm_gpio_set_value(&priv->reset_gpio, 1);
+
+		if (!do_reflection_test(dev)) {
+			printf("%s: Reflection test FAILED.\n", dev->name);
+			return -1;
+		}
+	}
+
+	printf("%s: Reflection test passed.\n", dev->name);
+
+	fpga_print_info(dev);
+
+	return 0;
+}
+
+static const struct udevice_id ihs_fpga_ids[] = {
+	{ .compatible = "gdsys,iocon_fpga" },
+	{ .compatible = "gdsys,iocpu_fpga" },
+	{ }
+};
+
+U_BOOT_DRIVER(ihs_fpga_bus) = {
+	.name           = "ihs_fpga_bus",
+	.id             = UCLASS_FPGAMAP,
+	.ops		= &ihs_fpga_ops,
+	.of_match       = ihs_fpga_ids,
+	.probe          = ihs_fpga_probe,
+	.priv_auto_alloc_size = sizeof(struct ihs_fpga_priv),
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index d774569cbc..b2e0cf2f83 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -263,5 +263,15 @@ config SYS_I2C_EEPROM_ADDR_OVERFLOW

 endif

+config GDSYS_IOEP
+	bool "Enable gdsys IOEP driver"
+	depends on MISC
+	help
+	  Support gdsys FPGA's IO endpoint driver.

+config GDSYS_SOC
+	bool "Enable gdsys SOC driver"
+	depends on MISC
+	help
+	  Support for IHS SOC.
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e8d598cd47..2e1c1021d2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -54,3 +54,5 @@ obj-$(CONFIG_QFW) += qfw.o
 obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
 obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
 obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
+obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
+obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c
new file mode 100644
index 0000000000..3ae0eb4209
--- /dev/null
+++ b/drivers/misc/gdsys_soc.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario.six at gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+
+#include "gdsys_soc.h"
+
+struct gdsys_soc_priv {
+	struct udevice *fpga;
+};
+
+static const struct udevice_id gdsys_soc_ids[] = {
+	{ .compatible = "gdsys,soc" },
+	{ /* sentinel */ }
+};
+
+int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga)
+{
+	struct gdsys_soc_priv *bus_priv;
+
+	if (!child->parent)
+		return -EINVAL;
+
+	if (!device_is_compatible(child->parent, "gdsys,soc"))
+		return -EINVAL;
+
+ 	bus_priv = dev_get_priv(child->parent);
+
+	*fpga = bus_priv->fpga;
+
+	return 0;
+}
+
+static int gdsys_soc_probe(struct udevice *dev)
+{
+	struct gdsys_soc_priv *priv = dev_get_priv(dev);
+	struct udevice *fpga;
+	int res = uclass_get_device_by_phandle(UCLASS_FPGAMAP, dev, "fpga",
+					       &fpga);
+	if (res == -ENOENT) {
+		printf("%s: Could not find 'fpga' phandle.\n", dev->name);
+		return -EINVAL;
+	}
+
+	if (res == -ENODEV) {
+		printf("%s: Could not get FPGA device.\n", dev->name);
+		return -EINVAL;
+	}
+
+	priv->fpga = fpga;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(gdsys_soc_bus) = {
+	.name           = "gdsys_soc_bus",
+	.id             = UCLASS_SIMPLE_BUS,
+	.of_match       = gdsys_soc_ids,
+	.probe          = gdsys_soc_probe,
+	.priv_auto_alloc_size = sizeof(struct gdsys_soc_priv),
+};
diff --git a/drivers/misc/gdsys_soc.h b/drivers/misc/gdsys_soc.h
new file mode 100644
index 0000000000..0f88149fd6
--- /dev/null
+++ b/drivers/misc/gdsys_soc.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario.six at gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GDSYS_SOC_H_
+#define _GDSYS_SOC_H_
+
+/**
+ * gdsys_soc_get_fpga() - Retrieve pointer to parent bus' FPGA device
+ *
+ * To access their register maps, devices on gdsys soc buses usually have
+ * facilitate the accessor function of the IHS FPGA their parent bus is
+ * attached to. To access the FPGA device from within the bus' children, this
+ * function returns a pointer to it.
+ *
+ * @child:	The child device on the FPGA bus needing access to the FPGA.
+ * @fpga:	Pointer to the retrieved FPGA device.
+ * @return 0 on success, -ve on failure
+ */
+int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga);
+#endif /* _GDSYS_SOC_H_ */
--
2.16.1



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