[U-Boot] [PATCH v7 06/35] musb: sunxi: Add OTG device clkgate and reset for H3/H5

[Marek Vasut]

On 05/07/2018 04:52 PM, Maxime Ripard wrote:
> On Mon, May 07, 2018 at 01:47:43PM +0200, Marek Vasut wrote:
>> On 05/07/2018 09:33 AM, Jagan Teki wrote:
>>> Add OTG device clkgate and reset for H3/H5 through driver_data.
>>>
>>> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
>>
>> Why don't you implement a clock driver for this SoC instead ?
> 
> Aren't you asking a bit too much?

I am not asking for anything, this is a question, not a request.

I asked why not implement a clock driver and use it just like any other
civilized modern driver would instead of digging in the clock controller
registers from a USB framework driver (which is icky).

I think that if we are doing some sort of conversion, we should do it
completely and properly instead of leaving in hacks like this. A clock
driver which allows enabling/disabling clock is probably like what, 2
hour work ? So maybe it's worth investing that time up front to save
maintenance burden in the future.

> Since the first post of these patches, you've asked to rework in a
> significant manner the driver already, including doing a new PHY
> driver to use the device model, and making other substantial changes
> to it.

Well yes, because it was crap at the beginning and I don't want to see
the crap accumulating. It has become much better since, as you can see I
only had a few minor comments.

> Jagan complied to all your requests so far, but this one is going to
> create yet another ton of patches on top of an (already) 35 patches
> series. And this request comes out of nowhere at the 7th version.

I disagree, one clock driver patch and a tweak to the series, unless I
missed something obvious.

> Creating a new clock driver will take a lot of effort, and this really
> surprise me given that we've had strictly no feedback from you on this
> considering all the previous SoCs bringups we've done so far.

What do you mean by "this" ? I think i did review the previous
iterations of this series ? If not, was I on CC ?

I have to admit, I don't really care about the rest of the Allwinner SoC
code or what you do there, I only care about the USB part and this
poking of clock controller registers seems wrong in a DM/DT driver.

I also don't mind if the clock driver comes later, but I would like to
see it happen at some point (soon) to remove this register poking.

-- 
Best regards,
Marek Vasut