[U-Boot] [PATCH 5/7] mach-snapdragon: Introduce pinctrl driver
Ramon Fried
ramon.fried at gmail.com
Sat May 12 10:15:56 UTC 2018
This patch adds pinmux and pinctrl driver for TLMM
subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is
generic and 8096 can be added easily.
Driver is using the generic dt-bindings and doesn't
introduce any new bindings (yet).
Signed-off-by: Ramon Fried <ramon.fried at gmail.com>
---
arch/arm/mach-snapdragon/Makefile | 2 +
arch/arm/mach-snapdragon/pinctrl-apq8016.c | 162 +++++++++++++++++++++++
arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 118 +++++++++++++++++
arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 21 +++
configs/dragonboard410c_defconfig | 5 +
include/dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 +++
6 files changed, 330 insertions(+)
create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c
create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c
create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h
create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 1c23dc52cf..1d35fea912 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -6,4 +6,6 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o
obj-y += clock-snapdragon.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/arch/arm/mach-snapdragon/pinctrl-apq8016.c
new file mode 100644
index 0000000000..8e57e2338c
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-apq8016.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8016 pinctrl
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried at gmail.com>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+const char * const msm_pinctrl_pins[] = {
+ "GPIO_0",
+ "GPIO_1",
+ "GPIO_2",
+ "GPIO_3",
+ "GPIO_4",
+ "GPIO_5",
+ "GPIO_6",
+ "GPIO_7",
+ "GPIO_8",
+ "GPIO_9",
+ "GPIO_10",
+ "GPIO_11",
+ "GPIO_12",
+ "GPIO_13",
+ "GPIO_14",
+ "GPIO_15",
+ "GPIO_16",
+ "GPIO_17",
+ "GPIO_18",
+ "GPIO_19",
+ "GPIO_20",
+ "GPIO_21",
+ "GPIO_22",
+ "GPIO_23",
+ "GPIO_24",
+ "GPIO_25",
+ "GPIO_26",
+ "GPIO_27",
+ "GPIO_28",
+ "GPIO_29",
+ "GPIO_30",
+ "GPIO_31",
+ "GPIO_32",
+ "GPIO_33",
+ "GPIO_34",
+ "GPIO_35",
+ "GPIO_36",
+ "GPIO_37",
+ "GPIO_38",
+ "GPIO_39",
+ "GPIO_40",
+ "GPIO_41",
+ "GPIO_42",
+ "GPIO_43",
+ "GPIO_44",
+ "GPIO_45",
+ "GPIO_46",
+ "GPIO_47",
+ "GPIO_48",
+ "GPIO_49",
+ "GPIO_50",
+ "GPIO_51",
+ "GPIO_52",
+ "GPIO_53",
+ "GPIO_54",
+ "GPIO_55",
+ "GPIO_56",
+ "GPIO_57",
+ "GPIO_58",
+ "GPIO_59",
+ "GPIO_60",
+ "GPIO_61",
+ "GPIO_62",
+ "GPIO_63",
+ "GPIO_64",
+ "GPIO_65",
+ "GPIO_66",
+ "GPIO_67",
+ "GPIO_68",
+ "GPIO_69",
+ "GPIO_70",
+ "GPIO_71",
+ "GPIO_72",
+ "GPIO_73",
+ "GPIO_74",
+ "GPIO_75",
+ "GPIO_76",
+ "GPIO_77",
+ "GPIO_78",
+ "GPIO_79",
+ "GPIO_80",
+ "GPIO_81",
+ "GPIO_82",
+ "GPIO_83",
+ "GPIO_84",
+ "GPIO_85",
+ "GPIO_86",
+ "GPIO_87",
+ "GPIO_88",
+ "GPIO_89",
+ "GPIO_90",
+ "GPIO_91",
+ "GPIO_92",
+ "GPIO_93",
+ "GPIO_94",
+ "GPIO_95",
+ "GPIO_96",
+ "GPIO_97",
+ "GPIO_98",
+ "GPIO_99",
+ "GPIO_100",
+ "GPIO_101",
+ "GPIO_102",
+ "GPIO_103",
+ "GPIO_104",
+ "GPIO_105",
+ "GPIO_106",
+ "GPIO_107",
+ "GPIO_108",
+ "GPIO_109",
+ "GPIO_110",
+ "GPIO_111",
+ "GPIO_112",
+ "GPIO_113",
+ "GPIO_114",
+ "GPIO_115",
+ "GPIO_116",
+ "GPIO_117",
+ "GPIO_118",
+ "GPIO_119",
+ "GPIO_120",
+ "GPIO_121",
+ "GPIO_122",
+ "GPIO_123",
+ "GPIO_124",
+ "GPIO_125",
+ "GPIO_126",
+ "GPIO_127",
+ "GPIO_128",
+ "GPIO_129",
+ "SDC1_CLK",
+ "SDC1_CMD",
+ "SDC1_DATA",
+ "SDC2_CLK",
+ "SDC2_CMD",
+ "SDC2_DATA",
+ "QDSD_CLK",
+ "QDSD_CMD",
+ "QDSD_DATA0",
+ "QDSD_DATA1",
+ "QDSD_DATA2",
+ "QDSD_DATA3",
+};
+
+const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"blsp1_uart", 2},
+};
+
+const int msm_functions_count = ARRAY_SIZE(msm_pinctrl_functions);
+const int msm_pins_count = ARRAY_SIZE(msm_pinctrl_pins);
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
new file mode 100644
index 0000000000..8aa6f9a7bd
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TLMM driver for Qualcomm APQ8016, APQ8096
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried at linaro.org>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include "pinctrl-snapdragon.h"
+
+struct msm_pinctrl_priv {
+ phys_addr_t base;
+};
+
+#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
+#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_ENABLE BIT(9)
+
+static const struct pinconf_param msm_conf_params[] = {
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+};
+
+static int msm_get_functions_count(struct udevice *dev)
+{
+ return msm_functions_count;
+}
+
+static int msm_get_pins_count(struct udevice *dev)
+{
+ return msm_pins_count;
+}
+
+static const char *msm_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static int msm_pinctrl_probe(struct udevice *dev)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->base = devfdt_get_addr(dev);
+
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+ return msm_pinctrl_pins[selector];
+}
+
+static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
+ unsigned int func_selector)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
+ msm_pinctrl_functions[func_selector].val << 2);
+ return 0;
+}
+
+static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
+ unsigned int param, unsigned int argument)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ TLMM_DRV_STRENGTH_MASK, argument << 6);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ TLMM_GPIO_PULL_MASK);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops msm_pinctrl_ops = {
+ .get_pins_count = msm_get_pins_count,
+ .get_pin_name = msm_get_pin_name,
+ .set_state = pinctrl_generic_set_state,
+ .pinmux_set = msm_pinmux_set,
+ .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
+ .pinconf_params = msm_conf_params,
+ .pinconf_set = msm_pinconf_set,
+ .get_functions_count = msm_get_functions_count,
+ .get_function_name = msm_get_function_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,tlmm-msm8916" },
+ { .compatible = "qcom,tlmm-apq8016" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_snapdraon) = {
+ .name = "pinctrl_msm",
+ .id = UCLASS_PINCTRL,
+ .of_match = msm_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
+ .ops = &msm_pinctrl_ops,
+ .probe = msm_pinctrl_probe,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
new file mode 100644
index 0000000000..3d0527148a
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm Pin control
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried at gmail.com>
+ *
+ */
+#ifndef _PINCTRL_SNAPDRAGON_H
+#define _PINCTRL_SNAPDRAGON_H
+
+struct pinctrl_function {
+ const char *name;
+ int val;
+};
+
+extern const char * const msm_pinctrl_pins[];
+extern const struct pinctrl_function msm_pinctrl_functions[];
+extern const int msm_functions_count;
+extern const int msm_pins_count;
+
+#endif
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index e6114db2ce..4b3de64dd5 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -45,3 +45,8 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+CONFIG_PINCTRL_GENERIC=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
new file mode 100644
index 0000000000..615affb6f2
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for Qualcomm Snapdragon pinctrl bindings.
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried at gmail.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+
+/* GPIO Drive Strength */
+#define DRIVE_STRENGTH_2MA 0
+#define DRIVE_STRENGTH_4MA 1
+#define DRIVE_STRENGTH_6MA 2
+#define DRIVE_STRENGTH_8MA 3
+#define DRIVE_STRENGTH_10MA 4
+#define DRIVE_STRENGTH_12MA 5
+#define DRIVE_STRENGTH_14MA 6
+#define DRIVE_STRENGTH_16MA 7
+
+#endif
--
2.14.1
More information about the U-Boot
mailing list