[U-Boot] [PATCH 1/3] x86: Change 4-level page table base address to low memory

[Alexander Graf]

> Am 01.02.2019 um 00:40 schrieb Bin Meng <bmeng.cn at gmail.com>:
> 
> Hi Alex,
> 
>> On Fri, Feb 1, 2019 at 2:30 AM Alexander Graf <agraf at suse.de> wrote:
>> 
>> 
>> 
>>> Am 31.01.2019 um 17:22 schrieb Bin Meng <bmeng.cn at gmail.com>:
>>> 
>>> At present the 4-level page table base address for 64-bit U-Boot
>>> proper is assigned an address that conflicts with CONFIG_LOADADDR.
>>> Change it to an address within the low memory range instead.
>> 
>> Can't you dynamically allocate the PT too?
>> 
> 
> The dynamically allocated PT only makes sense when in SPL. It then
> becomes an arbitrary address again when entering in the 64-bit proper.

I'm not sure I follow? On aarch64, we allocate every level dynamically. I feel like I'm missing a piece of the puzzle here :)

Alex

> 
> Regards,
> Bin