[U-Boot] [PATCH v3 6/6] net: phy: ar803x: Clarify the intention of ar8021_config

[Joe Hershberger]

On Fri, Jan 25, 2019 at 6:42 PM Vladimir Oltean <vladimir.oltean at nxp.com> wrote:
>
> Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
> the other bit positions, just like the other PHYs in the family do.
> Therefore, it is not necessary to hardcode the reserved values, but
> instead simply follow the read-modify-write procedure from the common
> function.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>

Acked-by: Joe Hershberger <joe.hreshberger at ni.com>