[U-Boot] [PATCH] arm: socfpga: move gen5 SDR driver to DM
marex at denx.de
Sat Feb 9 10:02:30 UTC 2019
On 2/8/19 11:51 PM, Dalon L Westergreen wrote:
> On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
>> Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
>> dalon.westergreen at linux.intel.com> geschrieben:
>>> On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote:
>>>> To clean up reset handling for socfpga gen5, let's move the code snippet
>>>> taking the DDR controller out of reset from SPL to the DDR driver.
>>>> While at it, port the ddr driver to UCLASS_RAM and use dts.
>>>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
>>>> This is an RFC to show what the SDRAM driver moved to DM (UCLASS_RAM)
>>>> look like. It's RFC both because Dinh did not seem too fond of changing
>>>> register address of the SDR in devicetree to include what the undocumented
>>>> registers 'sequencer.c' uses as well as because of my observed code
>>>> Basically, I want to move this to UCLASS_RAM and I want to read the reset
>>>> property for SDR from devicetree. What remains RFC is: do we want/need to
>>>> read the base address from devicetree, or can we live with it being hard-
>>>> coded (and maybe sanity-checked during probe)?
>>> My 2 cents, i love the idea of moving all of the socfgpa sdram code to DM.
>>> Looking at the code, i would suggest that we should handle the case where
>>> there is no HPS sdram controller, and instead an FPGA based controller is
>>> used. Although not common, it is a use case i have seen repeatedly.
>> While I haven't used it like that (I did use an FPGA RAM controller, but that
>> was with a NIOS and not Linux, not HPS), I guess it should work with my
>> changed. Just disable the 'sdr' node in the devicetree. You'll need a driver
>> for the FPGA based RAM controller though.
>> Or, in the setup you mentioned, would the existing driver be the same? I.e.
>> just use a different base address? Or is it a different IP?
> All you need is to have the h2f bridge enabled during the boot. We used to do
> this for you if spl found that the FPGA was already configured. On the FPGA
> side, a nios in the ddr controller runs the ddr calibration code.
This is stratix10 you're talking about, isn't it ? I recall S10 has
nios2 hard block to start up the DRAM, but Gen5 and A10 do not have
that, do they ?
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