[U-Boot] [PATCH] arm: socfpga: move gen5 SDR driver to DM

[Simon Goldschmidt]

Am 11.02.2019 um 19:38 schrieb Dalon L Westergreen:
> On Sat, 2019-02-09 at 11:02 +0100, Marek Vasut wrote:
>> On 2/8/19 11:51 PM, Dalon L Westergreen wrote:
>>> On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
>>>>
>>>> Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
>>>> dalon.westergreen at linux.intel.com> geschrieben:
>>>>> On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote:
> ...
>>>
>>> All you need is to have the h2f bridge enabled during the boot.  We used to
>>> do
>>> this for you if spl found that the FPGA was already configured.  On the FPGA
>>> side, a nios in the ddr controller runs the ddr calibration code.
>>
>> This is stratix10 you're talking about, isn't it ? I recall S10 has
>> nios2 hard block to start up the DRAM, but Gen5 and A10 do not have
>> that, do they ?
>>
> S10 and A10 both have a hard nios for ddr callibration, in cv / av for
> the soc emif, the A9 performs this functions, but for FPGA only DDR
> controllers there is a soft nios included in the FPGA ddr RTL that
> does the ddr callibration.  The cv/av code that does this is based
> on the soft nios core code that performs this function for fpga ddr
> controllers.

OK, thank you for this explanation!

So if I would use an FPGA-based SDRAM controller on cv, would this be 
the same driver (except for the calibration part) with a different base 
address? From reading the description I found, I thought it wouldn't?

Because this is where the discussion had started from Dalon: a 
FPGA-based SDRAM controller should now be possible when my patch is done 
and applied, but I guess it would need a different driver. My patch only 
ensures DM-based UCLASS_RAM drivers are probed.

Regards,
Simon