[U-Boot] [PATCH 4/7] riscv: delay initialization of caches and debug UART

Anup Patel Anup.Patel at wdc.com
Tue Feb 12 02:32:43 UTC 2019



> -----Original Message-----
> From: Lukas Auer [mailto:lukas.auer at aisec.fraunhofer.de]
> Sent: Tuesday, February 12, 2019 3:44 AM
> To: u-boot at lists.denx.de
> Cc: Atish Patra <Atish.Patra at wdc.com>; Anup Patel
> <Anup.Patel at wdc.com>; Bin Meng <bmeng.cn at gmail.com>; Andreas
> Schwab <schwab at suse.de>; Palmer Dabbelt <palmer at sifive.com>;
> Alexander Graf <agraf at suse.de>; Lukas Auer
> <lukas.auer at aisec.fraunhofer.de>; Rick Chen <rick at andestech.com>; Anup
> Patel <anup at brainfault.org>
> Subject: [PATCH 4/7] riscv: delay initialization of caches and debug UART
> 
> Move the initialization of the caches and the debug UART until after
> board_init_f_init_reserve. This is in preparation for SMP support, where
> code prior to this point will be executed by all harts. This ensures that
> initialization will only be performed once for the main hart running U-Boot.
> 
> Signed-off-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> ---
> 
>  arch/riscv/cpu/start.S | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index
> 81ea52b170..a30f6f7194 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -45,10 +45,6 @@ _start:
>  	/* mask all interrupts */
>  	csrw	MODE_PREFIX(ie), zero
> 
> -	/* Enable cache */
> -	jal	icache_enable
> -	jal	dcache_enable
> -
>  /*
>   * Set stackpointer in internal/ex RAM to call board_init_f
>   */
> @@ -57,10 +53,6 @@ call_board_init_f:
>  	li	t1, CONFIG_SYS_INIT_SP_ADDR
>  	and	sp, t1, t0		/* force 16 byte alignment */
> 
> -#ifdef CONFIG_DEBUG_UART
> -	jal	debug_uart_init
> -#endif
> -
>  call_board_init_f_0:
>  	mv	a0, sp
>  	jal	board_init_f_alloc_reserve
> @@ -74,6 +66,14 @@ call_board_init_f_0:
>  	/* save the boot hart id to global_data */
>  	SREG	s0, GD_BOOT_HART(gp)
> 
> +	/* Enable cache */
> +	jal	icache_enable
> +	jal	dcache_enable
> +
> +#ifdef CONFIG_DEBUG_UART
> +	jal	debug_uart_init
> +#endif
> +
>  	mv	a0, zero		/* a0 <-- boot_flags = 0 */
>  	la	t5, board_init_f
>  	jr	t5			/* jump to board_init_f() */
> --
> 2.20.1

Looks good to me.

Reviewed-by: Anup Patel <anup.patel at wdc.com>

Regards,
Anup



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