[U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

[Dalon L Westergreen]

On Tue, 2019-02-12 at 11:17 +0100, Marek Vasut wrote:
> On 2/12/19 11:13 AM, Chee, Tien Fong wrote:
> > On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> > > On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
> > > [...]
> > > 
> > > > > my preference for the fit image would be
> > > > > 
> > > > > ...
> > > > > images {
> > > > >   fpga at 1 {
> > > > > 	description = "FPGA Periph";
> > > > > 	...
> > > > > 	type = "fpga_periph";
> > > > > 	...
> > > > >   }
> > > > >   fpga at 2 {
> > > > > 	description = "FPGA Core";
> > > > > 	...
> > > > > 	type = "fpga" or
> > > > > "fpga_core";
> > > > I'm good with "fpga".
> > > > > 	...
> > > > >   }
> > > > > };
> > > > > configurations {
> > > > >   default = "config at 1"
> > > > >   config at 1 {
> > > > >       fpga = "fpga at 1";  // periph only
> > > > >   };
> > > > >   config at 2 {
> > > > >       fpga = "fpga at 1", "fpga at 2";
> > > > >   };
> > > > > };
> > > > > 
> > > > > with the expectation that the order of fpga at 1 and fpga at 2 in confi
> > > > > g at 2
> > > > > is not relevant.  the code should find the fpga_periph type and
> > > > > program
> > > > > it first.  just my comment, i dont like rellying on the order or
> > > > > name.
> > > > I can add support for above implementation although this adds more
> > > > complexity to the driver.
> > > You can have fpga node and e.g. fpga-name node in the configurations
> > > section to discern which phandle there is the core and which is the
> > > peripheral RBF. Would that work ?
> > > 
> > So something like that?
> > 
> > ...
> > 
> > images {
> >   fpga-periph at 1 {
> > 	description = "FPGA Periph";
> > 	...
> > 	type = "fpga_periph";
> 
> Do we need a new type for the periph/core distinction ?

not really, using the node name is fine with me as is shown below.
when i suggested that my intent was to allow the name to be
independant of the node name still envisioning scenarios where
the fit image has multiple fpga images.

> 
> > 	...
> >   }
> >   fpga-core at 2 {
> > 	description = "FPGA Core";
> > 	...
> > 	type = "fpga";
> > 	...
> >   }
> > };
> > configurations {
> >   default = "config at 1"
> >   config at 1 {
> >       fpga = "fpga-periph at 1";  // periph only
> >   };
> >   config at 2 {
> >       fpga = "fpga-periph at 1", "fpga-core at 2";
> >   };
> > };
> > 
> > > > Marek, are you OK with this implementation?
> > > Looks OK to me. Dalon ?
> > > 
> > > [...]
> 
>