[U-Boot] [PATCH 00/40] x86: Add support for booting from TPL

[Simon Glass]

Hi Bin,

On Wed, 30 Jan 2019 at 04:59, Simon Glass <sjg at chromium.org> wrote:
>
> At present SPL is used on 64-bit platforms, to allow SPL to be built as
> a 32-bit program and U-Boot proper to be built as 64-bit.
>
> However it is useful to be able to use SPL on any x86 platform, where
> U-Boot needs to be updated in the field. Then SPL can select which U-Boot
> to run (A or B) and most of the code can be updated. Similarly, using TPL
> allows both SPL and U-Boot to be updated. This is the best approach, since
> it means that all of U-Boot proper as well as SPL (in particular SDRAM
> init) can be updated in the field. This provides for the smallest possible
> amount of read-only (non-updateable) code: just the TPL code.
>
> This series contains a number of changes to allow x86 boards to use TPL,
> SPL and U-Boot proper. As a test, it is enabled for samus with a new
> chromebook_samus_tpl board.
>
>
> Simon Glass (40):
>   binman: Don't generate an error in 'text' entry constructor
>   binman: Don't show image-skip message by default
>   binman: Add a missing comment in Entry_vblock
>   dm: core: Fix translate condition in ofnode_get_addr_size()
>   cros_ec: Use a hyphen in the uclass name
>   spl: Allow sandbox to build a device-tree file
>   RFC: binman: Allow sections to have an offset
>   x86: start64: Fix copyright message
>   x86: mp_init: Use proper error numbers
>   x86: Add a way to reinit the cpu
>   x86: dts: Add device-tree labels for rtc and reset
>   x86: Update a stale comment about ifdtool
>   x86: Support SPL and TPL
>   x86: Support booting with TPL
>   x86: Add a handoff header file
>   x86: broadwell: Improve SDRAM debugging output
>   x86: broadwell: Allow SDRAM init from SPL
>   x86: Move init of debug UART to cpu.c
>   x86: broadwell: Split CPU init
>   x86: Add support for starting from SPL/TPL
>   x86: Allow 16-bit init to be in TPL
>   x86: broadwell: Allow booting from SPL
>   x86: broadwell: Select refcode and CPU code for SPL
>   x86: Add common Intel code for SPL
>   x86: Support saving MRC data from SPL
>   x86: Add a simple TPL implementations
>   x86: mrccache: Add more debugging
>   x86: Add a sysreset driver for the Intel PCH
>   x86: Support TPL in Intel common code
>   x86: Don't set up MTRRs in SPL
>   x86: Don't generate a bootstage report in SPL
>   x86: Support PCI VGA ROM when TPL is used
>   x86: sysreset: Implement the get_last() method
>   x86: Add documention on the samus flashmap
>   x86: samus: Update device tree for SPL
>   x86: samus: Update device tree for verified boot
>   x86: Update device tree for TPL
>   x86: Update device tree for Chromium OS verified boot
>   x86: Fix device-tree indentation
>   x86: samus: Add a target to boot through TPL

Just checking if you have any comments on this series?

Regards,
Simon