[U-Boot] [PATCH v8 0/8] Add support for loading FPGA bitstream

tien.fong.chee at intel.com tien.fong.chee at intel.com
Wed Feb 13 14:18:30 UTC 2019

From: Tien Fong Chee <tien.fong.chee at intel.com>

This version mainly resolved comments from Marek and Dalon L Westergreen in

Additonal note:
There are a few solutions at this moment for solving the performance issue
1. Using absolute data position to allign the core bistream in fitImage.
2. SPL program periph bitstream, then using fpga loadmk for loading the core
   bitstream from DDR. This is work because there is no allignment performance
   issue when reading whole fitImage instead of offset to the fitImage.

This series is working on top of u-boot.git -
 http://git.denx.de/u-boot.git .

[v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg314511.html

Tien Fong Chee (8):
  ARM: socfpga: Description on FPGA bitstream type and file name for
    Arria 10
  ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
  fit: Add function declarations to the header file
  ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
  ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
  spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
  ARM: socfpga: Synchronize the configuration for A10 SoCDK
  ARM: socfpga: Increase Malloc pool size to support FAT filesystem in

 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts       |  17 +
 .../include/mach/fpga_manager_arria10.h            |  39 +-
 arch/arm/mach-socfpga/spl_a10.c                    |  41 +-
 board/altera/arria10-socdk/fit_spl_fpga.its        |  39 ++
 configs/socfpga_arria10_defconfig                  |  21 +-
 .../fpga/altera-socfpga-a10-fpga-mgr.txt           |  26 +-
 drivers/fpga/socfpga_arria10.c                     | 467 ++++++++++++++++++++-
 include/configs/socfpga_common.h                   |   4 +-
 include/image.h                                    |   4 +
 9 files changed, 626 insertions(+), 32 deletions(-)
 create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its


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