[U-Boot] [PATCH 3/4] arm: mvebu: NAND clock support for MSYS devices

[Chris Packham]

One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.

Signed-off-by: Chris Packham <judge.packham at gmail.com>
---

 arch/arm/mach-mvebu/cpu.c              |  2 ++
 arch/arm/mach-mvebu/include/mach/soc.h | 11 +++++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index e80f9a86c483..770b437d15c1 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -500,6 +500,8 @@ u32 mvebu_get_nand_clock(void)
 
 	if (mvebu_soc_family() == MVEBU_SOC_A38X)
 		reg = MVEBU_DFX_DIV_CLK_CTRL(1);
+	else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
+		reg = MVEBU_DFX_DIV_CLK_CTRL(8);
 	else
 		reg = MVEBU_CORE_DIV_CLK_CTRL(1);
 
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index a7039516864e..efed55577b17 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -100,9 +100,20 @@
 #define SPI_PUP_EN		BIT(5)
 
 #define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
+#ifdef CONFIG_MSYS
+#define MVEBU_DFX_DIV_CLK_CTRL(i)	(MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
+#define NAND_ECC_DIVCKL_RATIO_OFFS	6
+#define NAND_ECC_DIVCKL_RATIO_MASK	(0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
 #define MVEBU_DFX_DIV_CLK_CTRL(i)	(MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
+#endif
+#ifdef CONFIG_MSYS
+#define NAND_ECC_DIVCKL_RATIO_OFFS	6
+#define NAND_ECC_DIVCKL_RATIO_MASK	(0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
 #define NAND_ECC_DIVCKL_RATIO_OFFS	8
 #define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
+#endif
 
 #define SDRAM_MAX_CS		4
 #define SDRAM_ADDR_MASK		0xFF000000
-- 
2.20.1