[U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs
Stefan Roese
sr at denx.de
Fri Feb 15 10:06:46 UTC 2019
Hi Chris,
On 15.02.19 10:41, Chris Packham wrote:
> Marvell's switch chips with integrated CPUs (collectively referred to as
> MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
> (e.g. xor) are located at different addresses and DFX server exists as a
> separate target on the MBUS (on Armada-38x it's just part of the core
> complex registers).
>
> Signed-off-by: Chris Packham <judge.packham at gmail.com>
> ---
>
> arch/arm/mach-mvebu/Kconfig | 18 ++++++++++++-
> arch/arm/mach-mvebu/Makefile | 1 +
> arch/arm/mach-mvebu/cpu.c | 32 +++++++++++++++++++++--
> arch/arm/mach-mvebu/include/mach/config.h | 2 +-
> arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++
> arch/arm/mach-mvebu/include/mach/soc.h | 20 ++++++++++++++
> drivers/ddr/marvell/axp/xor_regs.h | 4 +++
> 7 files changed, 76 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 7dda04e0e34e..05aa2ade0499 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -46,7 +46,7 @@ config ARMADA_8K
> # Armada PLL frequency (used for NAND clock generation)
> config SYS_MVEBU_PLL_CLOCK
> int
> - default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
> + default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || MSYS
I personally find this "MSYS" abbreviation quite short and not
descriptive. How is this handled (if at all yet) in Linux?
> default "1000000000" if ARMADA_38X || ARMADA_375
>
> # Armada XP/38x SoC types...
> @@ -63,6 +63,22 @@ config MV78460
> bool
> select ARMADA_XP
>
> +config MSYS
> + bool
> + select ARMADA_32BIT
> +
> +config 98DX4251
> + bool
> + select MSYS
> +
> +config 98DX3336
> + bool
> + select MSYS
> +
> +config 98DX3236
> + bool
> + select MSYS
> +
> config 88F6820
> bool
> select ARMADA_38X
> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
> index ee2eca913484..e7f1c59e6351 100644
> --- a/arch/arm/mach-mvebu/Makefile
> +++ b/arch/arm/mach-mvebu/Makefile
> @@ -24,6 +24,7 @@ ifndef CONFIG_SPL_BUILD
> obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
> obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
> obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
> +obj-$(CONFIG_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
> obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
>
> extra-y += kwbimage.cfg
> diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
> index 919d05c88c77..e80f9a86c483 100644
> --- a/arch/arm/mach-mvebu/cpu.c
> +++ b/arch/arm/mach-mvebu/cpu.c
> @@ -23,6 +23,12 @@ static struct mbus_win windows[] = {
> /* NOR */
> { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
> CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
> +
> +#ifdef CONFIG_MSYS
> + /* DFX */
> + { MBUS_DFX_BASE, MBUS_DFX_SIZE,
> + CPU_TARGET_DFX, 0 },
Nitpicking: Doesn't this fit into one single line?
> +#endif
> };
>
> void lowlevel_init(void)
> @@ -121,6 +127,14 @@ static const struct sar_freq_modes sar_freq_tab[] = {
> { 0x13, 0x0, 2000, 1000, 933 },
> { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
> };
> +#elif defined(CONFIG_MSYS)
> +static const struct sar_freq_modes sar_freq_tab[] = {
> + { 0x0, 0x0, 400, 400, 400 },
> + { 0x2, 0x0, 667, 333, 667 },
> + { 0x3, 0x0, 800, 400, 800 },
> + { 0x5, 0x0, 800, 400, 800 },
> + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
> +};
> #else
> /* SAR frequency values for Armada XP */
> static const struct sar_freq_modes sar_freq_tab[] = {
> @@ -144,7 +158,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
> u32 freq;
> int i;
>
> -#if defined(CONFIG_ARMADA_375)
> +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_MSYS)
> val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
> #else
> val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
> @@ -160,7 +174,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
> #endif
> for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
> if (sar_freq_tab[i].val == freq) {
> -#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
> +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined (CONFIG_MSYS)
> *sar_freq = sar_freq_tab[i];
> return;
> #else
> @@ -270,6 +284,20 @@ int print_cpuinfo(void)
> }
> }
>
> + if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
> + switch (revid) {
> + case 3:
> + puts("A0");
> + break;
> + case 4:
> + puts("A1");
> + break;
> + default:
> + printf("?? (%x)", revid);
> + break;
> + }
> + }
> +
> get_sar_freq(&sar_freq);
> printf(" at %d MHz\n", sar_freq.p_clk);
>
> diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
> index e3235fc67ecd..a78fbe5cc97b 100644
> --- a/arch/arm/mach-mvebu/include/mach/config.h
> +++ b/arch/arm/mach-mvebu/include/mach/config.h
> @@ -17,7 +17,7 @@
> #include <asm/arch/soc.h>
>
> #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
> - || defined(CONFIG_ARMADA_38X)
> + || defined(CONFIG_ARMADA_38X) || defined(CONFIG_MSYS)
> /*
> * Set this for the common xor register definitions needed in dram.c
> * for A38x as well here.
> diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
> index 9e23043a4857..b9153d86c669 100644
> --- a/arch/arm/mach-mvebu/include/mach/cpu.h
> +++ b/arch/arm/mach-mvebu/include/mach/cpu.h
> @@ -34,6 +34,7 @@ enum cpu_target {
> CPU_TARGET_PCIE02 = 0x4,
> CPU_TARGET_ETH01 = 0x7,
> CPU_TARGET_PCIE13 = 0x8,
> + CPU_TARGET_DFX = 0x8,
> CPU_TARGET_SASRAM = 0x9,
> CPU_TARGET_SATA01 = 0xa, /* A38X */
> CPU_TARGET_NAND = 0xd,
> @@ -79,6 +80,8 @@ enum {
> #define MBUS_PCI_IO_SIZE (64 << 10)
> #define MBUS_SPI_BASE 0xF4000000
> #define MBUS_SPI_SIZE (8 << 20)
> +#define MBUS_DFX_BASE 0xF6000000
> +#define MBUS_DFX_SIZE (1 << 20)
> #define MBUS_BOOTROM_BASE 0xF8000000
> #define MBUS_BOOTROM_SIZE (8 << 20)
>
> diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
> index 01577f469b0e..a7039516864e 100644
> --- a/arch/arm/mach-mvebu/include/mach/soc.h
> +++ b/arch/arm/mach-mvebu/include/mach/soc.h
> @@ -76,7 +76,11 @@
> #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
> #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
> #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
> +#ifdef CONFIG_MSYS
> +#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
> +#else
> #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
> +#endif
>
> #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
> #define MBUS_ERR_PROP_EN (1 << 8)
> @@ -149,6 +153,22 @@
> #define BOOT_FROM_SPI 0x32
> #define BOOT_FROM_MMC 0x30
> #define BOOT_FROM_MMC_ALT 0x31
> +#elif defined(CONFIG_MSYS)
> +/* SAR values for MSYS */
> +#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
> +#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
> +
> +#define SAR_CPU_FREQ_OFFS 18
> +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
> +#define SAR_BOOT_DEVICE_OFFS 11
> +#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
> +
> +#define BOOT_DEV_SEL_OFFS 11
> +#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
> +
> +#define BOOT_FROM_NAND 0x1
> +#define BOOT_FROM_UART 0x2
> +#define BOOT_FROM_SPI 0x3
> #else
> /* SAR values for Armada XP */
> #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
> diff --git a/drivers/ddr/marvell/axp/xor_regs.h b/drivers/ddr/marvell/axp/xor_regs.h
> index db5c41967393..bad41a3f3c1b 100644
> --- a/drivers/ddr/marvell/axp/xor_regs.h
> +++ b/drivers/ddr/marvell/axp/xor_regs.h
> @@ -13,7 +13,11 @@
> #define XOR_UNIT(chan) ((chan) >> 1)
> #define XOR_CHAN(chan) ((chan) & 1)
>
> +#ifdef CONFIG_MSYS
> +#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
> +#else
> #define MV_XOR_REGS_OFFSET(unit) (0x60900)
> +#endif
> #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
>
> /* XOR Engine Control Register Map */
>
More information about the U-Boot
mailing list