[U-Boot] [PATCH] L3 cache : arch : arm : lib : Flush L3 after relocation

[Stefan Roese]

Hi Prabhakar,

On 18.02.19 14:56, Prabhakar Kushwaha wrote:
> Hi Prafulla, Luka, Stefan, Tom and Albert
> 
>> -----Original Message-----
>> From: Meenakshi Aggarwal
>> Sent: Monday, February 18, 2019 7:16 PM
>> To: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; u-
>> boot at lists.denx.de; York Sun <york.sun at nxp.com>
>> Cc: Udit Kumar <udit.kumar at nxp.com>
>> Subject: RE: [PATCH] L3 cache : arch : arm : lib : Flush L3 after relocation
>>
>>
>>
>>> -----Original Message-----
>>> From: Prabhakar Kushwaha
>>> Sent: Monday, February 18, 2019 6:37 PM
>>> To: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>; u-
>>> boot at lists.denx.de; York Sun <york.sun at nxp.com>
>>> Cc: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>; Udit Kumar
>>> <udit.kumar at nxp.com>
>>> Subject: RE: [PATCH] L3 cache : arch : arm : lib : Flush L3 after
>>> relocation
>>>
>>>
>>>> -----Original Message-----
>>>> From: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
>>>> Sent: Tuesday, February 19, 2019 12:09 AM
>>>> To: u-boot at lists.denx.de; Prabhakar Kushwaha
>>>> <prabhakar.kushwaha at nxp.com>; York Sun <york.sun at nxp.com>
>>>> Cc: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>; Udit Kumar
>>>> <udit.kumar at nxp.com>
>>>> Subject: [PATCH] L3 cache : arch : arm : lib : Flush L3 after
>>>> relocation
>>>>
>>>> Flush L3 cache after uboot relocated to DDR.
>>>>
>>>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
>>>> Signed-off-by: Udit Kumar <udit.kumar at nxp.com>
>>>> ---
>>>>   arch/arm/lib/relocate_64.S | 1 +
>>>>   1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S
>>>> index
>>>> 171d094..7603f52 100644
>>>> --- a/arch/arm/lib/relocate_64.S
>>>> +++ b/arch/arm/lib/relocate_64.S
>>>> @@ -85,6 +85,7 @@ relocate_done:
>>>>   	isb	sy
>>>>   4:	ldp	x0, x1, [sp, #16]
>>>>   	bl	__asm_flush_dcache_range
>>>> +	bl     __asm_flush_l3_dcache
>>>
>>> This change is happening for every arm platform.
>>>
>>> There can be platform not having l3 cache. How It is taken care?
>>>
>> This function is defined as weak in arch/arm/cpu/armv8/cache.S for all other
>> platforms except
>>
>> arch/arm/mach-mvebu/armada8k/cache_llc.S
>> arch/arm/mach-tegra/tegra186/cache.S
> 
> Considering __asm_flush_l3_dcache is a weak function and only defined
> for armada, tegra and NXP.
> 
> This patch logically looks fine as after relocation to DDR, all cache
> should be flushed.
> Do you foresee any issue with this patch.

Looks fine to me as well (without testing). So:

Reviewed-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan