[U-Boot] [PATCH v6] lx2160aqds : Add support for LX2160AQDS platform

Prabhakar Kushwaha prabhakar.kushwaha at nxp.com
Wed Feb 20 07:48:02 UTC 2019


> -----Original Message-----
> From: Pankaj Bansal
> Sent: Friday, February 8, 2019 4:00 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>; Prabhakar
> Kushwaha <prabhakar.kushwaha at nxp.com>
> Cc: u-boot at lists.denx.de; Pankaj Bansal <pankaj.bansal at nxp.com>; Wasim
> Khan <wasim.khan at nxp.com>; Sriram Dash <sriram.dash at nxp.com>
> Subject: [PATCH v6] lx2160aqds : Add support for LX2160AQDS platform
> 
> LX2160AQDS is a development board that supports LX2160A
> family SoCs. This patch add base support for this board.
> 
> Signed-off-by: Wasim Khan <wasim.khan at nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash at nxp.com>
> Signed-off-by: Pankaj Bansal <pankaj.bansal at nxp.com>
> ---


This patch been applied to fsl-qoriq master, awaiting upstream.

--pk
	



> 
> Notes:
>     This patch depends on following patches:
>     	http://patchwork.ozlabs.org/patch/1030280/
>     V6
>     - Rebased on latest LX2160ARDB distro boot support patch
>     - Added 2019 in copyright
>     - Fixed some formatting errors.
>     V5
>     - Add "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" in
> phy
>       nodes for PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
>       specifications.
>     V4
>     - changed the LX2160ARDB to LX2160AQDS in dts file description
>       Also removed the Author info from dts file header
>       dts file : arch/arm/dts/fsl-lx2160a-qds.dts
>     V3
>     - modified the fdt phy fixup function as per fdt.
>       refer https://patchwork.codeaurora.org/patch/657515/
>     V2:
>     - removed checkpatch warnings about line over 80 chars
>     - Added CONFIG_FSL_MC_ENET macro in eth_lx2160aqds.c file
>       to avoid compilation errors if this macro is not defined
>     V1:
>     The checkpatch script reported 28 warnings about line over 80
>     characters, that i have not corrected. as IMO doing so, makes
>     the code less legible.
> 
>  arch/arm/Kconfig                             |  13 +
>  arch/arm/cpu/armv8/Kconfig                   |   1 +
>  arch/arm/dts/Makefile                        |   3 +-
>  arch/arm/dts/fsl-lx2160a-qds.dts             |  17 +
>  .../asm/arch-fsl-layerscape/immap_lsch3.h    |  10 +-
>  board/freescale/lx2160a/Kconfig              |  18 +
>  board/freescale/lx2160a/MAINTAINERS          |   9 +
>  board/freescale/lx2160a/Makefile             |   1 +
>  board/freescale/lx2160a/README               | 118 +++
>  board/freescale/lx2160a/eth_lx2160aqds.c     | 805 +++++++++++++++++
>  board/freescale/lx2160a/lx2160a.c            | 279 +++++-
>  configs/lx2160aqds_tfa_defconfig             |  72 ++
>  include/configs/lx2160aqds.h                 | 140 +++
>  13 files changed, 1483 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 6fb8e74f56..787695d3bd 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1090,6 +1090,19 @@ config TARGET_LX2160ARDB
>  	  is a high-performance development platform that supports the
>  	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture
> processor.
> 
> +config TARGET_LX2160AQDS
> +	bool "Support lx2160aqds"
> +	select ARCH_LX2160A
> +	select ARCH_MISC_INIT
> +	select ARM64
> +	select ARMV8_MULTIENTRY
> +	select BOARD_LATE_INIT
> +	help
> +	  Support for NXP LX2160AQDS platform.
> +	  The lx2160aqds (LX2160A QorIQ Development System (QDS)
> +	  is a high-performance development platform that supports the
> +	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture
> processor.
> +
>  config TARGET_HIKEY
>  	bool "Support HiKey 96boards Consumer Edition Platform"
>  	select ARM64
> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> index cc6d07832d..f0536038d6 100644
> --- a/arch/arm/cpu/armv8/Kconfig
> +++ b/arch/arm/cpu/armv8/Kconfig
> @@ -107,6 +107,7 @@ config PSCI_RESET
>  		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
>  		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
>  		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
> +		   !TARGET_LX2160AQDS && \
>  		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
>  	help
>  	  Most armv8 systems have PSCI support enabled in EL3, either
> through
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index dea689fdd3..276579c497 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -242,7 +242,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
>  	fsl-ls2088a-rdb-qspi.dtb \
>  	fsl-ls1088a-rdb.dtb \
>  	fsl-ls1088a-qds.dtb \
> -	fsl-lx2160a-rdb.dtb
> +	fsl-lx2160a-rdb.dtb \
> +	fsl-lx2160a-qds.dtb
>  dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
>  	fsl-ls1043a-qds-lpuart.dtb \
>  	fsl-ls1043a-rdb.dtb \
> diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-
> qds.dts
> new file mode 100644
> index 0000000000..6192156fc3
> --- /dev/null
> +++ b/arch/arm/dts/fsl-lx2160a-qds.dts
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * NXP LX2160AQDS device tree source
> + *
> + * Copyright 2018-2019 NXP
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-lx2160a.dtsi"
> +
> +/ {
> +	model = "NXP Layerscape LX2160AQDS Board";
> +	compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> +};
> +
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 0535224646..9fab88ab2f 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -2,7 +2,7 @@
>  /*
>   * LayerScape Internal Memory Map
>   *
> - * Copyright 2017-2018 NXP
> + * Copyright 2017-2019 NXP
>   * Copyright 2014 Freescale Semiconductor, Inc.
>   */
> 
> @@ -350,6 +350,14 @@ struct ccsr_gur {
>  #define FSL_CHASSIS3_SRDS1_REGSR	29
>  #define FSL_CHASSIS3_SRDS2_REGSR	29
>  #define FSL_CHASSIS3_SRDS3_REGSR	29
> +#define FSL_CHASSIS3_RCWSR12_REGSR         12
> +#define FSL_CHASSIS3_RCWSR13_REGSR         13
> +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK  0x07000000
> +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
> +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK  0x00000038
> +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
> +#define FSL_CHASSIS3_IIC5_PMUX_MASK        0x00000E00
> +#define FSL_CHASSIS3_IIC5_PMUX_SHIFT       9
>  #elif defined(CONFIG_ARCH_LS1088A)
>  #define FSL_CHASSIS3_EC1_REGSR  26
>  #define FSL_CHASSIS3_EC2_REGSR  26
> diff --git a/board/freescale/lx2160a/Kconfig
> b/board/freescale/lx2160a/Kconfig
> index 5562c3ec45..122a385100 100644
> --- a/board/freescale/lx2160a/Kconfig
> +++ b/board/freescale/lx2160a/Kconfig
> @@ -14,3 +14,21 @@ config SYS_CONFIG_NAME
> 
>  source "board/freescale/common/Kconfig"
>  endif
> +
> +if TARGET_LX2160AQDS
> +
> +config SYS_BOARD
> +	default "lx2160a"
> +
> +config SYS_VENDOR
> +	default "freescale"
> +
> +config SYS_SOC
> +	default "fsl-layerscape"
> +
> +config SYS_CONFIG_NAME
> +	default "lx2160aqds"
> +
> +source "board/freescale/common/Kconfig"
> +endif
> +
> diff --git a/board/freescale/lx2160a/MAINTAINERS
> b/board/freescale/lx2160a/MAINTAINERS
> index b4dd842afc..f2170a1772 100644
> --- a/board/freescale/lx2160a/MAINTAINERS
> +++ b/board/freescale/lx2160a/MAINTAINERS
> @@ -6,3 +6,12 @@ F:	include/configs/lx2160a_common.h
>  F:	include/configs/lx2160ardb.h
>  F:	configs/lx2160ardb_defconfig
>  F:	arch/arm/dts/fsl-lx2160a-rdb.dts
> +
> +LX2160AQDS BOARD
> +M:	Pankaj Bansal <pankaj.bansal at nxp.com>
> +S:	Maintained
> +F:	board/freescale/lx2160a/eth_lx2160aqds.h
> +F:	include/configs/lx2160aqds.h
> +F:	configs/lx2160aqds_tfa_defconfig
> +F:	arch/arm/dts/fsl-lx2160a-qds.dts
> +
> diff --git a/board/freescale/lx2160a/Makefile
> b/board/freescale/lx2160a/Makefile
> index be3709d449..d1a621b682 100644
> --- a/board/freescale/lx2160a/Makefile
> +++ b/board/freescale/lx2160a/Makefile
> @@ -7,3 +7,4 @@
>  obj-y += lx2160a.o
>  obj-y += ddr.o
>  obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
> +obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
> diff --git a/board/freescale/lx2160a/README
> b/board/freescale/lx2160a/README
> index 618c40b6fa..62fb9eab15 100644
> --- a/board/freescale/lx2160a/README
> +++ b/board/freescale/lx2160a/README
> @@ -77,3 +77,121 @@ DPAA2 MC Firmware
> 	0x05000
>  DPAA2 DPL						0x06800
>  DPAA2 DPC						0x07000
>  Kernel.itb						0x08000
> +
> +LX2160AQDS board Overview
> +----------------------
> +Various Mezzanine cards and their connection for different SERDES
> protocols is
> +as below:
> +
> +SERDES1	|CARDS
> +-----------------------------------------------------------------------
> +1	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
> +	|Connect I/O cable to IO_SLOT1(J110)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +3	|Mezzanine:X-M11-USXGMII (29828)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
> +	|Connect I/O cable to IO_SLOT1(J110)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +7	|Mezzanine:X-M11-USXGMII (29828)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
> +	|Connect I/O cable to IO_SLOT1(J110)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +8	|Mezzanine:X-M12-XFI (29829)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
> +	|Connect I/O cable to IO_SLOT1(J110)
> +	|Mezzanine:X-M12-XFI (29829)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +13	|Mezzanine:X-M8-100G (29734)
> +	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
> +	|Connect I/O cable to IO_SLOT1(J110)
> +	|Mezzanine:X-M8-100G (29734)
> +	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +15	|Mezzanine:X-M8-100G (29734)
> +	|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
> +	|Connect I/O cable to IO_SLOT1(J110)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +17	|Mezzanine:X-M13-25G  (32133)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
> +	|Connect I/O cable to IO_SLOT1(J110)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +19	|Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
> +	|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to
> IO_SLOT6(J125)
> +	|Mezzanine:X-M7-40G (29738)
> +	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +20	|Mezzanine:X-M7-40G (29738)
> +	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
> +	|Connect  I/O cable to IO_SLOT1(J108)
> +	|Mezzanine:X-M7-40G (29738)
> +	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
> +	|Connect I/O cable to IO_SLOT2(J113)
> +------------------------------------------------------------------------
> +
> +
> +SERDES2	|CARDS
> +-----------------------------------------------------------------------
> +2	|Mezzanine:X-M6-PCIE-X8 (29737) *
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
> +	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
> +	|Connect I/O cable to IO_SLOT3(J116)
> +------------------------------------------------------------------------
> +3	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
> +	|Connect I/O cable to IO_SLOT3(J116)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
> +	|Connect I/O cable to IO_SLOT4(J119)
> +------------------------------------------------------------------------
> +5	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
> +	|Connect I/O cable to IO_SLOT3(J116)
> +	|Mezzanine:X-M5-SATA (29687)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
> +	|Connect I/O cable to IO_SLOT4(J119)
> +------------------------------------------------------------------------
> +11	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
> +	|Connect I/O cable to IO_SLOT7(J127)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
> +	|Connect I/O cable to IO_SLOT8(J131)
> +------------------------------------------------------------------------
> +
> +
> +SERDES3	|CARDS
> +-----------------------------------------------------------------------
> +2	|Mezzanine:X-M6-PCIE-X8 (29737) *
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
> +	|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123)
> +	|Connect I/O cable to IO_SLOT5(J122)
> +-------------------------------------------------------------------------
> +3	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
> +	|Connect I/O cable to IO_SLOT5(J122)
> +	|Mezzanine:X-M4-PCIE-SGMII (29733)
> +	|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123)
> +	|Connect I/O cable to IO_SLOT6(J125)
> +-------------------------------------------------------------------------
> +
> diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c
> b/board/freescale/lx2160a/eth_lx2160aqds.c
> new file mode 100644
> index 0000000000..1e98d0c1f9
> --- /dev/null
> +++ b/board/freescale/lx2160a/eth_lx2160aqds.c
> @@ -0,0 +1,805 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018-2019 NXP
> + *
> + */
> +
> +#include <common.h>
> +#include <hwconfig.h>
> +#include <command.h>
> +#include <netdev.h>
> +#include <malloc.h>
> +#include <fsl_mdio.h>
> +#include <miiphy.h>
> +#include <phy.h>
> +#include <fm_eth.h>
> +#include <asm/io.h>
> +#include <exports.h>
> +#include <asm/arch/fsl_serdes.h>
> +#include <fsl-mc/fsl_mc.h>
> +#include <fsl-mc/ldpaa_wriop.h>
> +
> +#include "../common/qixis.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define EMI_NONE	0
> +#define EMI1		1 /* Mdio Bus 1 */
> +#define EMI2		2 /* Mdio Bus 2 */
> +
> +#if defined(CONFIG_FSL_MC_ENET)
> +enum io_slot {
> +	IO_SLOT_NONE = 0,
> +	IO_SLOT_1,
> +	IO_SLOT_2,
> +	IO_SLOT_3,
> +	IO_SLOT_4,
> +	IO_SLOT_5,
> +	IO_SLOT_6,
> +	IO_SLOT_7,
> +	IO_SLOT_8,
> +	EMI1_RGMII1,
> +	EMI1_RGMII2,
> +	IO_SLOT_MAX
> +};
> +
> +struct lx2160a_qds_mdio {
> +	enum io_slot ioslot : 4;
> +	u8 realbusnum : 4;
> +	struct mii_dev *realbus;
> +};
> +
> +/* structure explaining the phy configuration on 8 lanes of a serdes*/
> +struct serdes_phy_config {
> +	u8 serdes; /* serdes protocol */
> +	struct phy_config {
> +		u8 dpmacid;
> +		/* -1 terminated array */
> +		int phy_address[WRIOP_MAX_PHY_NUM + 1];
> +		u8 mdio_bus;
> +		enum io_slot ioslot;
> +	} phy_config[SRDS_MAX_LANES];
> +};
> +
> +/* Table defining the phy configuration on 8 lanes of a serdes.
> + * Various assumptions have been made while defining this table.
> + * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
> + * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
> + * And also that this card is connected to IO Slot 1 (could have been
> connected
> + * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
> + * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G
> card
> + * used in serdes1 protocol 19 (could have selected MDIO 2)
> + * To override these settings "dpmac" environment variable can be used
> after
> + * defining "dpmac_override" in hwconfig environment variable.
> + * This table has limited serdes protocol entries. It can be expanded as per
> + * requirement.
> + */
> +static const struct serdes_phy_config serdes1_phy_config[] = {
> +	{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
> +	      EMI1, IO_SLOT_1},
> +	    {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
> +	     EMI1, IO_SLOT_1},
> +	    {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
> +	     EMI1, IO_SLOT_1},
> +	    {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
> +	     EMI1, IO_SLOT_1} } },
> +	{7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
> +	      EMI1, IO_SLOT_1},
> +	    {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
> +	     EMI1, IO_SLOT_1},
> +	    {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
> +	     EMI1, IO_SLOT_1},
> +	    {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
> +	     EMI1, IO_SLOT_1},
> +	    {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
> +	     EMI1, IO_SLOT_2},
> +	    {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
> +	     EMI1, IO_SLOT_2},
> +	    {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
> +	     EMI1, IO_SLOT_2},
> +	    {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
> +	     EMI1, IO_SLOT_2} } },
> +	{8, {} },
> +	{13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -
> 1},
> +	       EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_2} } },
> +	{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -
> 1},
> +	       EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_1} } },
> +	{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -
> 1},
> +	       EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_1} } },
> +	{19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
> +	       EMI1, IO_SLOT_2},
> +	     {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
> +	      EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_6},
> +	     {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
> +	      EMI1, IO_SLOT_6} } },
> +	{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
> +	       EMI1, IO_SLOT_1},
> +	     {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
> +	      EMI1, IO_SLOT_2} } }
> +};
> +
> +static const struct serdes_phy_config serdes2_phy_config[] = {
> +	{2, {} },
> +	{3, {} },
> +	{5, {} },
> +	{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
> +	       EMI1, IO_SLOT_7},
> +	     {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
> +	      EMI1, IO_SLOT_7},
> +	     {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
> +	      EMI1, IO_SLOT_7},
> +	     {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
> +	      EMI1, IO_SLOT_8},
> +	     {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
> +	      EMI1, IO_SLOT_8},
> +	     {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
> +	      EMI1, IO_SLOT_8} } },
> +};
> +
> +static const struct serdes_phy_config serdes3_phy_config[] = {
> +	{2, {} },
> +	{3, {} }
> +};
> +
> +static inline
> +const struct phy_config *get_phy_config(u8 serdes,
> +					const struct serdes_phy_config
> *table,
> +					u8 table_size)
> +{
> +	int i;
> +
> +	for (i = 0; i < table_size; i++) {
> +		if (table[i].serdes == serdes)
> +			return table[i].phy_config;
> +	}
> +
> +	return NULL;
> +}
> +
> +/* BRDCFG4 controls EMI routing for the board.
> + * Bits    Function
> + * 7-6     EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
> + * EMI1    00= On-board PHY #1
> + *         01= On-board PHY #2
> + *         10= (reserved)
> + *         11= Slots 1..8 multiplexer and translator.
> + * 5-3     EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
> + * EMI1X   000= Slot #1
> + *         001= Slot #2
> + *         010= Slot #3
> + *         011= Slot #4
> + *         100= Slot #5
> + *         101= Slot #6
> + *         110= Slot #7
> + *         111= Slot #8
> + * 2-0     EMI Interface #2 Routing (CFG_MUX_EMI2):
> + * EMI2    000= Slot #1 (secondary EMI)
> + *         001= Slot #2 (secondary EMI)
> + *         010= Slot #3 (secondary EMI)
> + *         011= Slot #4 (secondary EMI)
> + *         100= Slot #5 (secondary EMI)
> + *         101= Slot #6 (secondary EMI)
> + *         110= Slot #7 (secondary EMI)
> + *         111= Slot #8 (secondary EMI)
> + */
> +static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot
> ioslot)
> +{
> +	switch (realbusnum) {
> +	case EMI1:
> +		switch (ioslot) {
> +		case EMI1_RGMII1:
> +			return 0;
> +		case EMI1_RGMII2:
> +			return 0x40;
> +		default:
> +			return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) |
> 0xC0);
> +		}
> +		break;
> +	case EMI2:
> +		return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
> +	default:
> +		return -1;
> +	}
> +}
> +
> +static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
> +{
> +	u8 brdcfg4, mux_val, reg;
> +
> +	brdcfg4 = QIXIS_READ(brdcfg[4]);
> +	reg = brdcfg4;
> +	mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv-
> >ioslot);
> +
> +	switch (priv->realbusnum) {
> +	case EMI1:
> +		brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
> +		brdcfg4 |= mux_val;
> +		break;
> +	case EMI2:
> +		brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
> +		brdcfg4 |= mux_val;
> +		break;
> +	}
> +
> +	if (brdcfg4 ^ reg)
> +		QIXIS_WRITE(brdcfg[4], brdcfg4);
> +}
> +
> +static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
> +				 int devad, int regnum)
> +{
> +	struct lx2160a_qds_mdio *priv = bus->priv;
> +
> +	lx2160a_qds_mux_mdio(priv);
> +
> +	return priv->realbus->read(priv->realbus, addr, devad, regnum);
> +}
> +
> +static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
> +				  int regnum, u16 value)
> +{
> +	struct lx2160a_qds_mdio *priv = bus->priv;
> +
> +	lx2160a_qds_mux_mdio(priv);
> +
> +	return priv->realbus->write(priv->realbus, addr, devad, regnum,
> value);
> +}
> +
> +static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
> +{
> +	struct lx2160a_qds_mdio *priv = bus->priv;
> +
> +	return priv->realbus->reset(priv->realbus);
> +}
> +
> +static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot
> ioslot)
> +{
> +	struct lx2160a_qds_mdio *pmdio;
> +	struct mii_dev *bus;
> +	/*should be within MDIO_NAME_LEN*/
> +	char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
> +
> +	if (realbusnum == EMI2) {
> +		if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
> +			printf("invalid ioslot %d\n", ioslot);
> +			return NULL;
> +		}
> +	} else if (realbusnum == EMI1) {
> +		if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
> +			printf("invalid ioslot %d\n", ioslot);
> +			return NULL;
> +		}
> +	} else {
> +		printf("not supported real mdio bus %d\n", realbusnum);
> +		return NULL;
> +	}
> +
> +	if (ioslot == EMI1_RGMII1)
> +		strcpy(dummy_mdio_name,
> "LX2160A_QDS_MDIO1_RGMII1");
> +	else if (ioslot == EMI1_RGMII2)
> +		strcpy(dummy_mdio_name,
> "LX2160A_QDS_MDIO1_RGMII2");
> +	else
> +		sprintf(dummy_mdio_name,
> "LX2160A_QDS_MDIO%d_IOSLOT%d",
> +			realbusnum, ioslot);
> +	bus = miiphy_get_dev_by_name(dummy_mdio_name);
> +
> +	if (bus)
> +		return bus;
> +
> +	bus = mdio_alloc();
> +	if (!bus) {
> +		printf("Failed to allocate %s bus\n", dummy_mdio_name);
> +		return NULL;
> +	}
> +
> +	pmdio = malloc(sizeof(*pmdio));
> +	if (!pmdio) {
> +		printf("Failed to allocate %s private data\n",
> dummy_mdio_name);
> +		free(bus);
> +		return NULL;
> +	}
> +
> +	switch (realbusnum) {
> +	case EMI1:
> +		pmdio->realbus =
> +
> miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
> +		break;
> +	case EMI2:
> +		pmdio->realbus =
> +
> miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
> +		break;
> +	}
> +
> +	if (!pmdio->realbus) {
> +		printf("No real mdio bus num %d found\n", realbusnum);
> +		free(bus);
> +		free(pmdio);
> +		return NULL;
> +	}
> +
> +	pmdio->realbusnum = realbusnum;
> +	pmdio->ioslot = ioslot;
> +	bus->read = lx2160a_qds_mdio_read;
> +	bus->write = lx2160a_qds_mdio_write;
> +	bus->reset = lx2160a_qds_mdio_reset;
> +	strcpy(bus->name, dummy_mdio_name);
> +	bus->priv = pmdio;
> +
> +	if (!mdio_register(bus))
> +		return bus;
> +
> +	printf("No bus with name %s\n", dummy_mdio_name);
> +	free(bus);
> +	free(pmdio);
> +	return NULL;
> +}
> +
> +static inline void do_phy_config(const struct phy_config *phy_config)
> +{
> +	struct mii_dev *bus;
> +	int i, phy_num, phy_address;
> +
> +	for (i = 0; i < SRDS_MAX_LANES; i++) {
> +		if (!phy_config[i].dpmacid)
> +			continue;
> +
> +		for (phy_num = 0;
> +		     phy_num < ARRAY_SIZE(phy_config[i].phy_address);
> +		     phy_num++) {
> +			phy_address =
> phy_config[i].phy_address[phy_num];
> +			if (phy_address == -1)
> +				break;
> +			wriop_set_phy_address(phy_config[i].dpmacid,
> +					      phy_num, phy_address);
> +		}
> +		/*Register the muxing front-ends to the MDIO buses*/
> +		bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
> +					    phy_config[i].ioslot);
> +		if (!bus)
> +			printf("could not get bus for mdio %d ioslot %d\n",
> +			       phy_config[i].mdio_bus,
> +			       phy_config[i].ioslot);
> +		else
> +			wriop_set_mdio(phy_config[i].dpmacid, bus);
> +	}
> +}
> +
> +static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
> +				   char *env_dpmac)
> +{
> +	const char *ret;
> +	size_t len;
> +	u8 realbusnum, ioslot;
> +	struct mii_dev *bus;
> +	int phy_num;
> +	char *phystr = "phy00";
> +
> +	/*search phy in dpmac arg*/
> +	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM;
> phy_num++) {
> +		sprintf(phystr, "phy%d", phy_num + 1);
> +		ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len,
> env_dpmac);
> +		if (!ret) {
> +			/*look for phy instead of phy1*/
> +			if (!phy_num)
> +				ret = hwconfig_subarg_f(arg_dpmacid,
> "phy",
> +							&len, env_dpmac);
> +			if (!ret)
> +				continue;
> +		}
> +
> +		if (len != 4 || strncmp(ret, "0x", 2))
> +			printf("invalid phy format in %s variable.\n"
> +			       "specify phy%d for %s in hex format e.g. 0x12\n",
> +			       env_dpmac, phy_num + 1, arg_dpmacid);
> +		else
> +			wriop_set_phy_address(dpmac, phy_num,
> +					      simple_strtoul(ret, NULL, 16));
> +	}
> +
> +	/*search mdio in dpmac arg*/
> +	ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
> +	if (ret)
> +		realbusnum = *ret - '0';
> +	else
> +		realbusnum = EMI_NONE;
> +
> +	if (realbusnum) {
> +		/*search io in dpmac arg*/
> +		ret = hwconfig_subarg_f(arg_dpmacid, "io", &len,
> env_dpmac);
> +		if (ret)
> +			ioslot = *ret - '0';
> +		else
> +			ioslot = IO_SLOT_NONE;
> +		/*Register the muxing front-ends to the MDIO buses*/
> +		bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
> +		if (!bus)
> +			printf("could not get bus for mdio %d ioslot %d\n",
> +			       realbusnum, ioslot);
> +		else
> +			wriop_set_mdio(dpmac, bus);
> +	}
> +}
> +
> +#endif
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#if defined(CONFIG_FSL_MC_ENET)
> +	struct memac_mdio_info mdio_info;
> +	struct memac_mdio_controller *regs;
> +	int i;
> +	const char *ret;
> +	char *env_dpmac;
> +	char dpmacid[] = "dpmac00", srds[] = "00_00_00";
> +	size_t len;
> +	struct mii_dev *bus;
> +	const struct phy_config *phy_config;
> +	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +	u32 srds_s1, srds_s2, srds_s3;
> +
> +	srds_s1 = in_le32(&gur->rcwsr[28]) &
> +		  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
> +	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
> +
> +	srds_s2 = in_le32(&gur->rcwsr[28]) &
> +		  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
> +	srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
> +
> +	srds_s3 = in_le32(&gur->rcwsr[28]) &
> +		  FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
> +	srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
> +
> +	sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
> +
> +	regs = (struct memac_mdio_controller
> *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
> +	mdio_info.regs = regs;
> +	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
> +
> +	/*Register the EMI 1*/
> +	fm_memac_mdio_init(bis, &mdio_info);
> +
> +	regs = (struct memac_mdio_controller
> *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
> +	mdio_info.regs = regs;
> +	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
> +
> +	/*Register the EMI 2*/
> +	fm_memac_mdio_init(bis, &mdio_info);
> +
> +	/* "dpmac" environment variable can be used after
> +	 * defining "dpmac_override" in hwconfig environment variable.
> +	 */
> +	if (hwconfig("dpmac_override")) {
> +		env_dpmac = env_get("dpmac");
> +		if (env_dpmac) {
> +			ret = hwconfig_arg_f("srds", &len, env_dpmac);
> +			if (ret) {
> +				if (strncmp(ret, srds, strlen(srds))) {
> +					printf("SERDES configuration
> changed.\n"
> +					       "previous: %.*s, current: %s.\n"
> +					       "update dpmac variable.\n",
> +					       (int)len, ret, srds);
> +				}
> +			} else {
> +				printf("SERDES configuration not found.\n"
> +				       "Please add srds:%s in dpmac variable\n",
> +				       srds);
> +			}
> +
> +			for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS;
> i++) {
> +				/* Look for dpmac1 to dpmac24(current max)
> arg
> +				 * in dpmac environment variable
> +				 */
> +				sprintf(dpmacid, "dpmac%d", i);
> +				ret = hwconfig_arg_f(dpmacid, &len,
> env_dpmac);
> +				if (ret)
> +					do_dpmac_config(i, dpmacid,
> env_dpmac);
> +			}
> +		} else {
> +			printf("Warning: environment dpmac not found.\n"
> +			       "DPAA network interfaces may not work\n");
> +		}
> +	} else {
> +		/*Look for phy config for serdes1 in phy config table*/
> +		phy_config = get_phy_config(srds_s1, serdes1_phy_config,
> +					    ARRAY_SIZE(serdes1_phy_config));
> +		if (!phy_config) {
> +			printf("%s WRIOP: Unsupported SerDes1 Protocol
> %d\n",
> +			       __func__, srds_s1);
> +		} else {
> +			do_phy_config(phy_config);
> +		}
> +		phy_config = get_phy_config(srds_s2, serdes2_phy_config,
> +					    ARRAY_SIZE(serdes2_phy_config));
> +		if (!phy_config) {
> +			printf("%s WRIOP: Unsupported SerDes2 Protocol
> %d\n",
> +			       __func__, srds_s2);
> +		} else {
> +			do_phy_config(phy_config);
> +		}
> +		phy_config = get_phy_config(srds_s3, serdes3_phy_config,
> +					    ARRAY_SIZE(serdes3_phy_config));
> +		if (!phy_config) {
> +			printf("%s WRIOP: Unsupported SerDes3 Protocol
> %d\n",
> +			       __func__, srds_s3);
> +		} else {
> +			do_phy_config(phy_config);
> +		}
> +	}
> +
> +	if (wriop_get_enet_if(WRIOP1_DPMAC17) ==
> PHY_INTERFACE_MODE_RGMII_ID) {
> +		wriop_set_phy_address(WRIOP1_DPMAC17, 0,
> RGMII_PHY_ADDR1);
> +		bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
> +		if (!bus)
> +			printf("could not get bus for RGMII1\n");
> +		else
> +			wriop_set_mdio(WRIOP1_DPMAC17, bus);
> +	}
> +
> +	if (wriop_get_enet_if(WRIOP1_DPMAC18) ==
> PHY_INTERFACE_MODE_RGMII_ID) {
> +		wriop_set_phy_address(WRIOP1_DPMAC18, 0,
> RGMII_PHY_ADDR2);
> +		bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
> +		if (!bus)
> +			printf("could not get bus for RGMII2\n");
> +		else
> +			wriop_set_mdio(WRIOP1_DPMAC18, bus);
> +	}
> +
> +	cpu_eth_init(bis);
> +#endif /* CONFIG_FMAN_ENET */
> +
> +#ifdef CONFIG_PHY_AQUANTIA
> +	/*
> +	 * Export functions to be used by AQ firmware
> +	 * upload application
> +	 */
> +	gd->jt->strcpy = strcpy;
> +	gd->jt->mdelay = mdelay;
> +	gd->jt->mdio_get_current_dev = mdio_get_current_dev;
> +	gd->jt->phy_find_by_mask = phy_find_by_mask;
> +	gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
> +	gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
> +#endif
> +	return pci_eth_init(bis);
> +}
> +
> +#if defined(CONFIG_RESET_PHY_R)
> +void reset_phy(void)
> +{
> +#if defined(CONFIG_FSL_MC_ENET)
> +	mc_env_boot();
> +#endif
> +}
> +#endif /* CONFIG_RESET_PHY_R */
> +
> +#if defined(CONFIG_FSL_MC_ENET)
> +int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int
> node_phandle)
> +{
> +	int offset;
> +	int ret;
> +	char dpmac_str[] = "dpmacs at 00";
> +	const char *phy_string;
> +
> +	offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
> +
> +	if (offset < 0)
> +		offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
> +
> +	if (offset < 0) {
> +		printf("dpmacs node not found in device tree\n");
> +		return offset;
> +	}
> +
> +	sprintf(dpmac_str, "dpmac@%x", dpmac_id);
> +	debug("dpmac_str = %s\n", dpmac_str);
> +
> +	offset = fdt_subnode_offset(fdt, offset, dpmac_str);
> +	if (offset < 0) {
> +		printf("%s node not found in device tree\n", dpmac_str);
> +		return offset;
> +	}
> +
> +	ret = fdt_appendprop_cell(fdt, offset, "phy-handle",
> node_phandle);
> +	if (ret)
> +		printf("%d@%s %d\n", __LINE__, __func__, ret);
> +
> +	phy_string =
> phy_string_for_interface(wriop_get_enet_if(dpmac_id));
> +	ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
> +				 phy_string);
> +	if (ret)
> +		printf("%d@%s %d\n", __LINE__, __func__, ret);
> +
> +	return ret;
> +}
> +
> +int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int
> fpga_offset)
> +{
> +	char mdio_ioslot_str[] = "mdio at 00";
> +	char mdio_mux_str[] = "mdio-mux-0";
> +	struct lx2160a_qds_mdio *priv;
> +	int offset, mux_val;
> +
> +	/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
> +	if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
> +		    strlen("LX2160A_QDS_MDIO")))
> +		return -1;
> +
> +	/*Get the real MDIO bus num and ioslot info from bus's priv data*/
> +	priv = mii_dev->priv;
> +
> +	debug("real_bus_num = %d, ioslot = %d\n",
> +	      priv->realbusnum, priv->ioslot);
> +
> +	sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
> +	offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
> +	if (offset < 0) {
> +		printf("%s node not found under node %s in device tree\n",
> +		       mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
> +		return offset;
> +	}
> +
> +	mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv-
> >ioslot);
> +	sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
> +
> +	offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
> +	if (offset < 0) {
> +		printf("%s node not found in device tree\n",
> mdio_ioslot_str);
> +		return offset;
> +	}
> +
> +	return offset;
> +}
> +
> +int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int
> *subnodeoffset,
> +			struct phy_device *phy_dev, int phandle)
> +{
> +	char phy_node_name[] = "ethernet-phy at 00";
> +	char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
> +	int ret;
> +
> +	sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
> +	debug("phy_node_name = %s\n", phy_node_name);
> +
> +	*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
> +	if (*subnodeoffset <= 0) {
> +		printf("Could not add subnode %s\n", phy_node_name);
> +		return *subnodeoffset;
> +	}
> +
> +	sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
> +		phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
> +	debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
> +
> +	ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
> +				 phy_id_compatible_str);
> +	if (ret) {
> +		printf("%d@%s %d\n", __LINE__, __func__, ret);
> +		goto out;
> +	}
> +
> +	if (phy_dev->is_c45) {
> +		ret = fdt_appendprop_string(fdt, *subnodeoffset,
> "compatible",
> +					    "ethernet-phy-ieee802.3-c45");
> +		if (ret) {
> +			printf("%d@%s %d\n", __LINE__, __func__, ret);
> +			goto out;
> +		}
> +	} else {
> +		ret = fdt_appendprop_string(fdt, *subnodeoffset,
> "compatible",
> +					    "ethernet-phy-ieee802.3-c22");
> +		if (ret) {
> +			printf("%d@%s %d\n", __LINE__, __func__, ret);
> +			goto out;
> +		}
> +	}
> +
> +	ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
> +	if (ret) {
> +		printf("%d@%s %d\n", __LINE__, __func__, ret);
> +		goto out;
> +	}
> +
> +	ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
> +	if (ret) {
> +		printf("%d@%s %d\n", __LINE__, __func__, ret);
> +		goto out;
> +	}
> +
> +out:
> +	if (ret)
> +		fdt_del_node(fdt, *subnodeoffset);
> +
> +	return ret;
> +}
> +
> +int fdt_fixup_board_phy(void *fdt)
> +{
> +	int fpga_offset, offset, subnodeoffset;
> +	struct mii_dev *mii_dev;
> +	struct list_head *mii_devs, *entry;
> +	int ret, dpmac_id, phandle, i;
> +	struct phy_device *phy_dev;
> +	char ethname[ETH_NAME_LEN];
> +	phy_interface_t	phy_iface;
> +
> +	ret = 0;
> +	/* we know FPGA is connected to i2c0, therefore search path
> directly,
> +	 * instead of compatible property, as it saves time
> +	 */
> +	fpga_offset = fdt_path_offset(fdt, "/soc/i2c at 2000000/fpga");
> +
> +	if (fpga_offset < 0)
> +		fpga_offset = fdt_path_offset(fdt, "/i2c at 2000000/fpga");
> +
> +	if (fpga_offset < 0) {
> +		printf("i2c at 2000000/fpga node not found in device tree\n");
> +		return fpga_offset;
> +	}
> +
> +	phandle = fdt_alloc_phandle(fdt);
> +	mii_devs = mdio_get_list_head();
> +
> +	list_for_each(entry, mii_devs) {
> +		mii_dev = list_entry(entry, struct mii_dev, link);
> +		debug("mii_dev name : %s\n", mii_dev->name);
> +		offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
> +		if (offset < 0)
> +			continue;
> +
> +		// Look for phy devices attached to MDIO bus muxing front
> end
> +		// and create their entries with compatible being the device
> id
> +		for (i = 0; i < PHY_MAX_ADDR; i++) {
> +			phy_dev = mii_dev->phymap[i];
> +			if (!phy_dev)
> +				continue;
> +
> +			// TODO: use sscanf instead of loop
> +			dpmac_id = WRIOP1_DPMAC1;
> +			while (dpmac_id < NUM_WRIOP_PORTS) {
> +				phy_iface = wriop_get_enet_if(dpmac_id);
> +				snprintf(ethname, ETH_NAME_LEN,
> "DPMAC%d@%s",
> +					 dpmac_id,
> +
> phy_string_for_interface(phy_iface));
> +				if (strcmp(ethname, phy_dev->dev->name)
> == 0)
> +					break;
> +				dpmac_id++;
> +			}
> +			if (dpmac_id == NUM_WRIOP_PORTS)
> +				continue;
> +
> +			ret = fdt_create_phy_node(fdt, offset, i,
> +						  &subnodeoffset,
> +						  phy_dev, phandle);
> +			if (ret)
> +				break;
> +
> +			ret = fdt_fixup_dpmac_phy_handle(fdt,
> +							 dpmac_id, phandle);
> +			if (ret) {
> +				fdt_del_node(fdt, subnodeoffset);
> +				break;
> +			}
> +			phandle++;
> +		}
> +
> +		if (ret)
> +			break;
> +	}
> +
> +	return ret;
> +}
> +#endif // CONFIG_FSL_MC_ENET
> +
> diff --git a/board/freescale/lx2160a/lx2160a.c
> b/board/freescale/lx2160a/lx2160a.c
> index a62222e25c..2cbfe4806b 100644
> --- a/board/freescale/lx2160a/lx2160a.c
> +++ b/board/freescale/lx2160a/lx2160a.c
> @@ -26,6 +26,18 @@
>  #include "../common/vid.h"
>  #include <fsl_immap.h>
> 
> +#ifdef CONFIG_TARGET_LX2160AQDS
> +#define CFG_MUX_I2C_SDHC(reg, value)		((reg & 0x3f) | value)
> +#define SET_CFG_MUX1_SDHC1_SDHC(reg)		(reg & 0x3f)
> +#define SET_CFG_MUX2_SDHC1_SPI(reg, value)	((reg & 0xcf) | value)
> +#define SET_CFG_MUX3_SDHC1_SPI(reg, value)	((reg & 0xf8) | value)
> +#define SET_CFG_MUX_SDHC2_DSPI(reg, value)	((reg & 0xf8) | value)
> +#define SET_CFG_MUX1_SDHC1_DSPI(reg, value)	((reg & 0x3f) | value)
> +#define SDHC1_BASE_PMUX_DSPI			2
> +#define SDHC2_BASE_PMUX_DSPI			2
> +#define IIC5_PMUX_SPI3				3
> +#endif /* CONFIG_TARGET_LX2160AQDS */
> +
>  DECLARE_GLOBAL_DATA_PTR;
> 
>  static struct pl01x_serial_platdata serial0 = {
> @@ -85,12 +97,80 @@ int board_early_init_f(void)
>  	return 0;
>  }
> 
> +#if defined(CONFIG_TARGET_LX2160AQDS)
> +void esdhc_dspi_status_fixup(void *blob)
> +{
> +	const char esdhc0_path[] = "/soc/esdhc at 2140000";
> +	const char esdhc1_path[] = "/soc/esdhc at 2150000";
> +	const char dspi0_path[] = "/soc/dspi at 2100000";
> +	const char dspi1_path[] = "/soc/dspi at 2110000";
> +	const char dspi2_path[] = "/soc/dspi at 2120000";
> +
> +	struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +	u32 sdhc1_base_pmux;
> +	u32 sdhc2_base_pmux;
> +	u32 iic5_pmux;
> +
> +	/* Check RCW field sdhc1_base_pmux to enable/disable
> +	 * esdhc0/dspi0 DT node
> +	 */
> +	sdhc1_base_pmux = gur_in32(&gur-
> >rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
> +		& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
> +	sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
> +
> +	if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
> +		do_fixup_by_path(blob, dspi0_path, "status", "okay",
> +				 sizeof("okay"), 1);
> +		do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
> +				 sizeof("disabled"), 1);
> +	} else {
> +		do_fixup_by_path(blob, esdhc0_path, "status", "okay",
> +				 sizeof("okay"), 1);
> +		do_fixup_by_path(blob, dspi0_path, "status", "disabled",
> +				 sizeof("disabled"), 1);
> +	}
> +
> +	/* Check RCW field sdhc2_base_pmux to enable/disable
> +	 * esdhc1/dspi1 DT node
> +	 */
> +	sdhc2_base_pmux = gur_in32(&gur-
> >rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
> +		& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
> +	sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
> +
> +	if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
> +		do_fixup_by_path(blob, dspi1_path, "status", "okay",
> +				 sizeof("okay"), 1);
> +		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
> +				 sizeof("disabled"), 1);
> +	} else {
> +		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
> +				 sizeof("okay"), 1);
> +		do_fixup_by_path(blob, dspi1_path, "status", "disabled",
> +				 sizeof("disabled"), 1);
> +	}
> +
> +	/* Check RCW field IIC5 to enable dspi2 DT node */
> +	iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR
> - 1])
> +		& FSL_CHASSIS3_IIC5_PMUX_MASK;
> +	iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
> +
> +	if (iic5_pmux == IIC5_PMUX_SPI3) {
> +		do_fixup_by_path(blob, dspi2_path, "status", "okay",
> +				 sizeof("okay"), 1);
> +	}
> +}
> +#endif
> +
>  int esdhc_status_fixup(void *blob, const char *compat)
>  {
> +#if defined(CONFIG_TARGET_LX2160AQDS)
> +	/* Enable esdhc and dspi DT nodes based on RCW fields */
> +	esdhc_dspi_status_fixup(blob);
> +#else
>  	/* Enable both esdhc DT nodes for LX2160ARDB */
>  	do_fixup_by_compat(blob, compat, "status", "okay",
>  			   sizeof("okay"), 1);
> -
> +#endif
>  	return 0;
>  }
> 
> @@ -107,9 +187,20 @@ int checkboard(void)
>  	enum boot_src src = get_boot_src();
>  	char buf[64];
>  	u8 sw;
> +#ifdef CONFIG_TARGET_LX2160AQDS
> +	int clock;
> +	static const char *const freq[] = {"100", "125", "156.25",
> +					   "161.13", "322.26", "", "", "",
> +					   "", "", "", "", "", "", "",
> +					   "100 separate SSCG"};
> +#endif
> 
>  	cpu_name(buf);
> +#ifdef CONFIG_TARGET_LX2160AQDS
> +	printf("Board: %s-QDS, ", buf);
> +#else
>  	printf("Board: %s-RDB, ", buf);
> +#endif
> 
>  	sw = QIXIS_READ(arch);
>  	printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
> @@ -136,22 +227,206 @@ int checkboard(void)
>  			break;
>  		}
>  	}
> +#ifdef CONFIG_TARGET_LX2160AQDS
> +	printf("FPGA: v%d (%s), build %d",
> +	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
> +	       (int)qixis_read_minor());
> +	/* the timestamp string contains "\n" at the end */
> +	printf(" on %s", qixis_read_time(buf));
> +
> +	puts("SERDES1 Reference : ");
> +	sw = QIXIS_READ(brdcfg[2]);
> +	clock = sw >> 4;
> +	printf("Clock1 = %sMHz ", freq[clock]);
> +	clock = sw & 0x0f;
> +	printf("Clock2 = %sMHz", freq[clock]);
> +
> +	sw = QIXIS_READ(brdcfg[3]);
> +	puts("\nSERDES2 Reference : ");
> +	clock = sw >> 4;
> +	printf("Clock1 = %sMHz ", freq[clock]);
> +	clock = sw & 0x0f;
> +	printf("Clock2 = %sMHz", freq[clock]);
> +
> +	sw = QIXIS_READ(brdcfg[12]);
> +	puts("\nSERDES3 Reference : ");
> +	clock = sw >> 4;
> +	printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
> +#else
>  	printf("FPGA: v%d.%d\n", QIXIS_READ(scver),
> QIXIS_READ(tagdata));
> 
>  	puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 =
> 161.13MHz\n");
>  	puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
>  	puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
> +#endif
>  	return 0;
>  }
> 
> +#ifdef CONFIG_TARGET_LX2160AQDS
> +/*
> + * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
> + */
> +u8 qixis_esdhc_detect_quirk(void)
> +{
> +	/* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status
> (SDHC1)
> +	 * SDHC1 Card ID:
> +	 * Specifies the type of card installed in the SDHC1 adapter slot.
> +	 * 000= (reserved)
> +	 * 001= eMMC V4.5 adapter is installed.
> +	 * 010= SD/MMC 3.3V adapter is installed.
> +	 * 011= eMMC V4.4 adapter is installed.
> +	 * 100= eMMC V5.0 adapter is installed.
> +	 * 101= MMC card/Legacy (3.3V) adapter is installed.
> +	 * 110= SDCard V2/V3 adapter installed.
> +	 * 111= no adapter is installed.
> +	 */
> +	return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
> +		 QIXIS_ESDHC_NO_ADAPTER);
> +}
> +
> +int config_board_mux(void)
> +{
> +	u8 reg11, reg5, reg13;
> +	struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +	u32 sdhc1_base_pmux;
> +	u32 sdhc2_base_pmux;
> +	u32 iic5_pmux;
> +
> +	/* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B,
> SDHC1_WP}.
> +	 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as
> {CAN1_TX,CAN1_RX}.
> +	 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as
> {CAN2_TX,CAN2_RX}.
> +	 * Qixis and remote systems are isolated from the I2C1 bus.
> +	 * Processor connections are still available.
> +	 * SPI2 CS2_B controls EN25S64 SPI memory device.
> +	 * SPI3 CS2_B controls EN25S64 SPI memory device.
> +	 * EC2 connects to PHY #2 using RGMII protocol.
> +	 * CLK_OUT connects to FPGA for clock measurement.
> +	 */
> +
> +	reg5 = QIXIS_READ(brdcfg[5]);
> +	reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
> +	QIXIS_WRITE(brdcfg[5], reg5);
> +
> +	/* Check RCW field sdhc1_base_pmux
> +	 * esdhc0 : sdhc1_base_pmux = 0
> +	 * dspi0  : sdhc1_base_pmux = 2
> +	 */
> +	sdhc1_base_pmux = gur_in32(&gur-
> >rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
> +		& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
> +	sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
> +
> +	if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
> +		reg11 = QIXIS_READ(brdcfg[11]);
> +		reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
> +		QIXIS_WRITE(brdcfg[11], reg11);
> +	} else {
> +		/* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter
> slot.
> +		 *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
> +		 *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
> +		 */
> +		reg11 = QIXIS_READ(brdcfg[11]);
> +		reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
> +		QIXIS_WRITE(brdcfg[11], reg11);
> +	}
> +
> +	/* Check RCW field sdhc2_base_pmux
> +	 * esdhc1 : sdhc2_base_pmux = 0 (default)
> +	 * dspi1  : sdhc2_base_pmux = 2
> +	 */
> +	sdhc2_base_pmux = gur_in32(&gur-
> >rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
> +		& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
> +	sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
> +
> +	if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
> +		reg13 = QIXIS_READ(brdcfg[13]);
> +		reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
> +		QIXIS_WRITE(brdcfg[13], reg13);
> +	} else {
> +		reg13 = QIXIS_READ(brdcfg[13]);
> +		reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
> +		QIXIS_WRITE(brdcfg[13], reg13);
> +	}
> +
> +	/* Check RCW field IIC5 to enable dspi2 DT nodei
> +	 * dspi2: IIC5 = 3
> +	 */
> +	iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR
> - 1])
> +		& FSL_CHASSIS3_IIC5_PMUX_MASK;
> +	iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
> +
> +	if (iic5_pmux == IIC5_PMUX_SPI3) {
> +		/* - Routes {SDHC1_DAT4} to SPI3 devices as
> {SPI3_M_CS0_B}. */
> +		reg11 = QIXIS_READ(brdcfg[11]);
> +		reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
> +		QIXIS_WRITE(brdcfg[11], reg11);
> +
> +		/* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
> +		 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
> +		 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI,
> SPI3_M0_MISO}.
> +		 */
> +		reg11 = QIXIS_READ(brdcfg[11]);
> +		reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
> +		QIXIS_WRITE(brdcfg[11], reg11);
> +	} else {
> +		/*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
> +		reg11 = QIXIS_READ(brdcfg[11]);
> +		reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
> +		QIXIS_WRITE(brdcfg[11], reg11);
> +
> +		/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter
> slot.
> +		 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
> +		 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
> +		 */
> +		reg11 = QIXIS_READ(brdcfg[11]);
> +		reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
> +		QIXIS_WRITE(brdcfg[11], reg11);
> +	}
> +
> +	return 0;
> +}
> +#else
> +int config_board_mux(void)
> +{
> +	return 0;
> +}
> +#endif
> +
>  unsigned long get_board_sys_clk(void)
>  {
> +#ifdef CONFIG_TARGET_LX2160AQDS
> +	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
> +
> +	switch (sysclk_conf & 0x03) {
> +	case QIXIS_SYSCLK_100:
> +		return 100000000;
> +	case QIXIS_SYSCLK_125:
> +		return 125000000;
> +	case QIXIS_SYSCLK_133:
> +		return 133333333;
> +	}
> +	return 100000000;
> +#else
>  	return 100000000;
> +#endif
>  }
> 
>  unsigned long get_board_ddr_clk(void)
>  {
> +#ifdef CONFIG_TARGET_LX2160AQDS
> +	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
> +
> +	switch ((ddrclk_conf & 0x30) >> 4) {
> +	case QIXIS_DDRCLK_100:
> +		return 100000000;
> +	case QIXIS_DDRCLK_125:
> +		return 125000000;
> +	case QIXIS_DDRCLK_133:
> +		return 133333333;
> +	}
> +	return 100000000;
> +#else
>  	return 100000000;
> +#endif
>  }
> 
>  int board_init(void)
> @@ -184,6 +459,8 @@ void detail_board_ddr_info(void)
>  #if defined(CONFIG_ARCH_MISC_INIT)
>  int arch_misc_init(void)
>  {
> +	config_board_mux();
> +
>  	return 0;
>  }
>  #endif
> diff --git a/configs/lx2160aqds_tfa_defconfig
> b/configs/lx2160aqds_tfa_defconfig
> new file mode 100644
> index 0000000000..7914dbecd5
> --- /dev/null
> +++ b/configs/lx2160aqds_tfa_defconfig
> @@ -0,0 +1,72 @@
> +CONFIG_ARM=y
> +CONFIG_TARGET_LX2160AQDS=y
> +CONFIG_SYS_TEXT_BASE=0x82000000
> +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
> +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
> +CONFIG_NR_DRAM_BANKS=3
> +CONFIG_DM=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_OF_STDOUT_VIA_ALIAS=y
> +CONFIG_TFABOOT=y
> +CONFIG_BOOTDELAY=10
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0
> earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000
> default_hugepagesz=1024m hugepagesz=1024m hugepages=2
> pci=pcie_bus_perf"
> +# CONFIG_USE_BOOTCOMMAND is not set
> +CONFIG_CMD_GREPENV=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_MP=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_CONS_INDEX=0
> +CONFIG_FSL_CAAM=y
> +CONFIG_FSL_ESDHC=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_NXP_FSPI=y
> +CONFIG_FSPI_AHB_EN_4BYTE=y
> +CONFIG_SYS_FSPI_AHB_INIT=y
> +CONFIG_PHYLIB=y
> +CONFIG_NETDEVICES=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_CMD_NET=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_PXE=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_NET=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
> +CONFIG_SCSI_AHCI=y
> +CONFIG_SCSI=y
> +# CONFIG_SYS_FSL_DDR_PHY is not set
> +CONFIG_SYS_GEN2_DDR_PHY=y
> +CONFIG_SYS_MALLOC_F=y
> +CONFIG_SYS_MALLOC_F_LEN=0x6000
> +CONFIG_PHYLIB_10G=y
> +CONFIG_PHY_AQUANTIA=y # X-M11-USXGMII
> +CONFIG_PHY_CORTINA=y # X-M7-40G
> +CONFIG_PHY_REALTEK=y # RGMII
> +CONFIG_PHY_INPHI=y # X-M8-100G
> +CONFIG_PHY_VITESSE=y # SGMII PEX RISER
> +CONFIG_HUSH_PARSER=y
> diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
> new file mode 100644
> index 0000000000..82cd471a8e
> --- /dev/null
> +++ b/include/configs/lx2160aqds.h
> @@ -0,0 +1,140 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018-2019 NXP
> + */
> +
> +#ifndef __LX2_QDS_H
> +#define __LX2_QDS_H
> +
> +#include "lx2160a_common.h"
> +
> +/* Qixis */
> +#define QIXIS_XMAP_MASK			0x07
> +#define QIXIS_XMAP_SHIFT		5
> +#define QIXIS_RST_CTL_RESET_EN		0x30
> +#define QIXIS_LBMAP_DFLTBANK		0x00
> +#define QIXIS_LBMAP_ALTBANK		0x20
> +#define QIXIS_LBMAP_QSPI		0x00
> +#define QIXIS_RCW_SRC_QSPI		0xff
> +#define QIXIS_RST_CTL_RESET		0x31
> +#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
> +#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
> +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
> +#define QIXIS_LBMAP_MASK		0x0f
> +#define QIXIS_LBMAP_SD
> +#define QIXIS_RCW_SRC_SD           	0x08
> +#define NON_EXTENDED_DUTCFG
> +#define QIXIS_SDID_MASK			0x07
> +#define QIXIS_ESDHC_NO_ADAPTER		0x7
> +
> +/* SYSCLK */
> +#define QIXIS_SYSCLK_100		0x0
> +#define QIXIS_SYSCLK_125		0x1
> +#define QIXIS_SYSCLK_133		0x2
> +
> +/* DDRCLK */
> +#define QIXIS_DDRCLK_100		0x0
> +#define QIXIS_DDRCLK_125		0x1
> +#define QIXIS_DDRCLK_133		0x2
> +
> +#define BRDCFG4_EMI1SEL_MASK		0xF8
> +#define BRDCFG4_EMI1SEL_SHIFT		3
> +#define BRDCFG4_EMI2SEL_MASK		0x07
> +#define BRDCFG4_EMI2SEL_SHIFT		0
> +
> +/* VID */
> +
> +#define I2C_MUX_CH_VOL_MONITOR		0xA
> +/* Voltage monitor on channel 2*/
> +#define I2C_VOL_MONITOR_ADDR		0x63
> +#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
> +#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
> +#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
> +#define CONFIG_VID_FLS_ENV		"lx2160aqds_vdd_mv"
> +#define CONFIG_VID
> +
> +/* The lowest and highest voltage allowed*/
> +#define VDD_MV_MIN			775
> +#define VDD_MV_MAX			925
> +
> +/* PM Bus commands code for LTC3882*/
> +#define PMBUS_CMD_PAGE                  0x0
> +#define PMBUS_CMD_READ_VOUT             0x8B
> +#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
> +#define PMBUS_CMD_VOUT_COMMAND          0x21
> +#define PWM_CHANNEL0                    0x0
> +
> +#define CONFIG_VOL_MONITOR_LTC3882_SET
> +#define CONFIG_VOL_MONITOR_LTC3882_READ
> +
> +/* RTC */
> +#define CONFIG_SYS_RTC_BUS_NUM		0
> +#define I2C_MUX_CH_RTC			0xB
> +
> +/*
> + * MMC
> + */
> +#ifdef CONFIG_MMC
> +#ifndef __ASSEMBLY__
> +u8 qixis_esdhc_detect_quirk(void);
> +#endif
> +#define CONFIG_ESDHC_DETECT_QUIRK  qixis_esdhc_detect_quirk()
> +#endif
> +
> +/* MAC/PHY configuration */
> +#if defined(CONFIG_FSL_MC_ENET)
> +#define CONFIG_MII
> +#define CONFIG_ETHPRIME		"DPMAC17 at rgmii-id"
> +
> +#define AQ_PHY_ADDR1		0x00
> +#define AQ_PHY_ADDR2		0x01
> +#define AQ_PHY_ADDR3		0x02
> +#define AQ_PHY_ADDR4		0x03
> +
> +#define CORTINA_NO_FW_UPLOAD
> +#define CORTINA_PHY_ADDR1	0x0
> +
> +#define INPHI_PHY_ADDR1		0x0
> +#define INPHI_PHY_ADDR2		0x1
> +
> +#define RGMII_PHY_ADDR1		0x01
> +#define RGMII_PHY_ADDR2		0x02
> +
> +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
> +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
> +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
> +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
> +
> +#endif
> +
> +/* EEPROM */
> +#define CONFIG_ID_EEPROM
> +#define CONFIG_SYS_I2C_EEPROM_NXID
> +#define CONFIG_SYS_EEPROM_BUS_NUM		0
> +#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
> +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS		\
> +	EXTRA_ENV_SETTINGS			\
> +	"lx2160aqds_vdd_mv=800\0"		\
> +	"BOARD=lx2160aqds\0"			\
> +	"xspi_bootcmd=echo Trying load from flexspi..;"		\
> +		"sf probe 0:0 && sf read $load_addr "		\
> +		"$kernel_start $kernel_size ; env exists secureboot &&"
> 	\
> +		"sf read $kernelheader_addr_r $kernelheader_start "	\
> +		"$kernelheader_size && esbc_validate
> ${kernelheader_addr_r}; "\
> +		" bootm $load_addr#$BOARD\0"			\
> +	"sd_bootcmd=echo Trying load from sd card..;"		\
> +		"mmcinfo; mmc read $load_addr "			\
> +		"$kernel_addr_sd $kernel_size_sd ;"		\
> +		"env exists secureboot && mmc read $kernelheader_addr_r
> "\
> +		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
> +		" && esbc_validate ${kernelheader_addr_r};"	\
> +		"bootm $load_addr#$BOARD\0"
> +
> +#include <asm/fsl_secure_boot.h>
> +
> +#endif /* __LX2_QDS_H */
> --
> 2.17.1



More information about the U-Boot mailing list