[U-Boot] [PATCH v2 1/8] arm: socfpga: gen5: sync devicetrees to Linux
Simon Goldschmidt
simon.k.r.goldschmidt at gmail.com
Thu Feb 21 22:02:10 UTC 2019
Am Do., 21. Feb. 2019, 22:56 hat Marek Vasut <marex at denx.de> geschrieben:
> On 2/21/19 10:43 PM, Simon Goldschmidt wrote:
> > This is again a sync to linux-next + pending patches in Dinh's tree at
> > commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset
> > properties")'
> >
> > It adds missing peripheral reset properties to socfpga.dtsi and removes
> > U-Boot specific leftovers from socfpga_cyclone5_socrates.dts.
> >
> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> > ---
> >
> > Changes in v2:
> > - cleanly merged Linux dts (moved change of SDR controller base address
> > to a separate patch)
> >
> > arch/arm/dts/socfpga.dtsi | 19 +++++++++++++++++--
> > arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 --
> > 2 files changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> > index 2458d6707d..ec1966480f 100644
> > --- a/arch/arm/dts/socfpga.dtsi
> > +++ b/arch/arm/dts/socfpga.dtsi
> > @@ -84,6 +84,7 @@
> > #dma-requests = <32>;
> > clocks = <&l4_main_clk>;
> > clock-names = "apb_pclk";
> > + resets = <&rst DMA_RESET>;
> > };
> > };
> >
> > @@ -100,6 +101,7 @@
> > reg = <0xffc00000 0x1000>;
> > interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0
> 134 4>;
> > clocks = <&can0_clk>;
> > + resets = <&rst CAN0_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -108,6 +110,7 @@
> > reg = <0xffc01000 0x1000>;
> > interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0
> 138 4>;
> > clocks = <&can1_clk>;
> > + resets = <&rst CAN1_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -585,6 +588,7 @@
> > compatible = "snps,dw-apb-gpio";
> > reg = <0xff708000 0x1000>;
> > clocks = <&l4_mp_clk>;
> > + resets = <&rst GPIO0_RESET>;
> > status = "disabled";
> >
> > porta: gpio-controller at 0 {
> > @@ -605,6 +609,7 @@
> > compatible = "snps,dw-apb-gpio";
> > reg = <0xff709000 0x1000>;
> > clocks = <&l4_mp_clk>;
> > + resets = <&rst GPIO1_RESET>;
> > status = "disabled";
> >
> > portb: gpio-controller at 0 {
> > @@ -625,6 +630,7 @@
> > compatible = "snps,dw-apb-gpio";
> > reg = <0xff70a000 0x1000>;
> > clocks = <&l4_mp_clk>;
> > + resets = <&rst GPIO2_RESET>;
> > status = "disabled";
> >
> > portc: gpio-controller at 0 {
> > @@ -735,6 +741,7 @@
> > #size-cells = <0>;
> > clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
> > clock-names = "biu", "ciu";
> > + resets = <&rst SDMMC_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -746,9 +753,9 @@
> > <0xffb80000 0x10000>;
> > reg-names = "nand_data", "denali_reg";
> > interrupts = <0x0 0x90 0x4>;
> > - dma-mask = <0xffffffff>;
> > clocks = <&nand_clk>, <&nand_x_clk>,
> <&nand_ecc_clk>;
> > clock-names = "nand", "nand_x", "ecc";
> > + resets = <&rst NAND_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -759,7 +766,7 @@
> >
> > qspi: spi at ff705000 {
> > compatible = "cdns,qspi-nor";
> > - #address-cells = <1>;
> > + #address-cells = <1>;
> > #size-cells = <0>;
> > reg = <0xff705000 0x1000>,
> > <0xffa00000 0x1000>;
> > @@ -768,6 +775,7 @@
> > cdns,fifo-width = <4>;
> > cdns,trigger-address = <0x00000000>;
> > clocks = <&qspi_clk>;
> > + resets = <&rst QSPI_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -786,6 +794,7 @@
> > sdr: sdr at ffc25000 {
> > compatible = "altr,sdr-ctl", "syscon";
> > reg = <0xffc25000 0x1000>;
> > + resets = <&rst SDR_RESET>;
> > };
> >
> > sdramedac {
> > @@ -802,6 +811,7 @@
> > interrupts = <0 154 4>;
> > num-cs = <4>;
> > clocks = <&spi_m_clk>;
> > + resets = <&rst SPIM0_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -813,6 +823,7 @@
> > interrupts = <0 155 4>;
> > num-cs = <4>;
> > clocks = <&spi_m_clk>;
> > + resets = <&rst SPIM1_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -879,6 +890,7 @@
> > dmas = <&pdma 28>,
> > <&pdma 29>;
> > dma-names = "tx", "rx";
> > + resets = <&rst UART0_RESET>;
> > };
> >
> > uart1: serial1 at ffc03000 {
> > @@ -891,6 +903,7 @@
> > dmas = <&pdma 30>,
> > <&pdma 31>;
> > dma-names = "tx", "rx";
> > + resets = <&rst UART1_RESET>;
> > };
> >
> > usbphy0: usbphy {
> > @@ -930,6 +943,7 @@
> > reg = <0xffd02000 0x1000>;
> > interrupts = <0 171 4>;
> > clocks = <&osc1>;
> > + resets = <&rst L4WD0_RESET>;
> > status = "disabled";
> > };
> >
> > @@ -938,6 +952,7 @@
> > reg = <0xffd03000 0x1000>;
> > interrupts = <0 172 4>;
> > clocks = <&osc1>;
> > + resets = <&rst L4WD1_RESET>;
> > status = "disabled";
> > };
> > };
> > diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts
> b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> > index 93c3fa4a48..8d5d3996f6 100644
> > --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
> > +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> > @@ -76,7 +76,6 @@
> >
> > &qspi {
> > status = "okay";
> > - u-boot,dm-pre-reloc;
> >
> > flash: flash at 0 {
> > #address-cells = <1>;
> > @@ -91,6 +90,5 @@
> > cdns,tchsh-ns = <4>;
> > cdns,tslch-ns = <4>;
> > status = "okay";
> > - u-boot,dm-pre-reloc;
>
> Is this intended ?
>
Yes, see the commit message. We have it in a U-Boot specific overlay and
this is a sync to Linux patch.
Regards,
Simon
> > };
> > };
> >
>
>
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