[U-Boot] [PATCH v3 1/7] ARM: k2g-ice: Add pinmux support for rgmii interface

[Joe Hershberger]

On Thu, Feb 21, 2019 at 11:03 AM Murali Karicheri <m-karicheri2 at ti.com> wrote:
>
> This add pinmux configuration for rgmii interface so that network
> driver can be supported on K2G ICE boards. The pinmux configurations
> for this are generated using the pinmux tool at
> https://dev.ti.com/pinmux/app.html#/default
>
> As this required some BUFFER_CLASS definitions, same is re-used
> from the linux defnitions in include/dt-bindings/pinctrl/keystone.h
>
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
> Reviewed-by: Lokesh Vutla <lokeshvutla at ti.com>
> ---
>  arch/arm/mach-keystone/include/mach/mux-k2g.h |  5 +++++
>  board/ti/ks2_evm/mux-k2g.h                    | 19 +++++++++++++++++++
>  2 files changed, 24 insertions(+)
>
> diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h b/arch/arm/mach-keystone/include/mach/mux-k2g.h
> index 809b72d5bf..67d47f8172 100644
> --- a/arch/arm/mach-keystone/include/mach/mux-k2g.h
> +++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h
> @@ -27,6 +27,11 @@
>  #define PIN_PTU        (1 << 17) /* pull up */
>  #define PIN_PTD        (0 << 17) /* pull down */
>
> +#define BUFFER_CLASS_B (0 << 19)
> +#define BUFFER_CLASS_C (1 << 19)
> +#define BUFFER_CLASS_D (2 << 19)
> +#define BUFFER_CLASS_E (3 << 19)
> +
>  #define MODE(m)        ((m) & 0x7)
>  #define MAX_PIN_N      260
>
> diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
> index 706fb7e838..8c184a85ae 100644
> --- a/board/ti/ks2_evm/mux-k2g.h
> +++ b/board/ti/ks2_evm/mux-k2g.h
> @@ -346,6 +346,25 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = {
>         { 133,  MODE(0) },      /* SOC_QSPI_D2 */
>         { 134,  MODE(0) },      /* SOC_QSPI_D3 */
>         { 135,  MODE(0) },      /* SOC_QSPI_CSN0 */
> +
> +       /* EMAC */
> +       { 79,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD1 */
> +       { 78,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD2 */
> +       { 77,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD3 */
> +       { 80,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXD0 */
> +       { 94,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD0 */
> +       { 93,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD1 */
> +       { 92,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD2 */
> +       { 91,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXD3 */
> +       { 85,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXC */
> +       { 95,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_TXCTL */
> +       { 72,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXC */
> +       { 81,   BUFFER_CLASS_D | PIN_PDIS | MODE(1) },  /* RGMII_RXCTL */

Actually... please sort these by pin number.

Thanks,
-Joe

> +
> +       /* MDIO */
> +       { 99,   BUFFER_CLASS_B | PIN_PDIS | MODE(0) },  /* MDIO_CLK */
> +       { 98,   BUFFER_CLASS_B | PIN_PDIS | MODE(0) },  /* MDIO_DATA */
> +
>         { MAX_PIN_N, }
>  };
>
> --
> 2.17.0
>
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