[U-Boot] [PATCH v9 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

Michal Simek monstr at monstr.eu
Tue Feb 26 15:42:13 UTC 2019


On 26. 02. 19 15:28, Chee, Tien Fong wrote:
> On Tue, 2019-02-26 at 15:06 +0100, Michal Simek wrote:
>> On 19. 02. 19 4:47, tien.fong.chee at intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee at intel.com>
>>>
>>> This patch adds description on properties about file name used for
>>> both
>>> peripheral bitstream and core bitstream.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
>>>
>>> ---
>>>
>>> changes for v8
>>> - Removed explanation about support for altr,bitstream-core
>>>
>>> changes for v7
>>> - Provided example of setting FPGA FIT image for both early IO
>>> release
>>>   and full release FPGA configuration.
>>> ---
>>>  .../fpga/altera-socfpga-a10-fpga-mgr.txt           | 26
>>> +++++++++++++++++++++-
>>>  1 file changed, 25 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>> mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
>>> mgr.txt
>>> index 2fd8e7a..da210bf 100644
>>> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
>>> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
>>> @@ -7,8 +7,31 @@ Required properties:
>>>                 - The second index is for writing FPGA
>>> configuration data.
>>>  - resets     : Phandle and reset specifier for the device's reset.
>>>  - clocks     : Clocks used by the device.
>>> +- altr,bitstream : Fit image file name for both FPGA peripheral
>>> bitstream,
>>> +		   FPGA core bitstream and full bitstream.
>>>  
>> By adding new required property you are automatically saying that you
>> want to break all current users.
> This is company's product specific property, that's why with prefix
> "altr". DT allows that ,right?

no issue with altr prefix. Issue is that you add a required property and
breaking all current users.
It should be optional.

M



-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs


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