[U-Boot] Marvell DDR training custom ODT configuration

[Baruch Siach]

Hi Chris,

Currently the value of g_odt_config is hard coded in Marvell SoC
platform headers. Some SolidRun A388 SOMs need a custom value. These
SOMs use both DDR chip-selects, but ODT0 alone is connected to both
chips. For that to work we need to set g_odt_config to 0x30000, that is,
ODT0 is configured for both CS0 and CS1.

How can we do that in a clean way so as to not interfere too much with
your periodic code syncs from Marvell's DDR training source tree?

Thanks,
baruch

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