[U-Boot] [PATCH v6 1/6] pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family

Daniel Schwierzeck daniel.schwierzeck at gmail.com
Sat Jan 12 16:38:35 UTC 2019



Am 11.01.19 um 23:31 schrieb Horatiu Vultur:
> The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common
> to support new numbe of pins and remove any platform dependency from
> mscc-common.
> 
> Signed-off-by: Horatiu Vultur <horatiu.vultur at microchip.com>
> ---
>  MAINTAINERS                           |   1 +
>  drivers/pinctrl/mscc/Kconfig          |   9 +
>  drivers/pinctrl/mscc/Makefile         |   1 +
>  drivers/pinctrl/mscc/mscc-common.c    |  90 +++++++---
>  drivers/pinctrl/mscc/mscc-common.h    |  17 +-
>  drivers/pinctrl/mscc/pinctrl-jr2.c    | 323 ++++++++++++++++++++++++++++++++++
>  drivers/pinctrl/mscc/pinctrl-luton.c  |  16 +-
>  drivers/pinctrl/mscc/pinctrl-ocelot.c |  16 +-
>  8 files changed, 444 insertions(+), 29 deletions(-)
>  create mode 100644 drivers/pinctrl/mscc/pinctrl-jr2.c

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>

only some nits left

> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 494962e..495d3e5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -525,6 +525,7 @@ F:	board/mscc/
>  F:	configs/mscc*
>  F:	drivers/gpio/mscc_sgpio.c
>  F:	include/configs/vcoreiii.h
> +F:	drivers/pinctrl/mscc/
>  
>  MIPS JZ4780
>  M:	Ezequiel Garcia <ezequiel at collabora.com>
> diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
> index cfc6c06..d07ea1b 100644
> --- a/drivers/pinctrl/mscc/Kconfig
> +++ b/drivers/pinctrl/mscc/Kconfig
> @@ -20,3 +20,12 @@ config PINCTRL_MSCC_LUTON
>  	help
>  	   Support pin multiplexing and pin configuration control on
>  	   Microsemi luton SoCs.
> +
> +config PINCTRL_MSCC_JR2
> +	depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
> +	select PINCTRL_MSCC
> +	default y
> +	bool "Microsemi jr2 family pin control driver"
> +	help
> +	    Support pin multiplexing and pin configuration control on
> +	    Microsemi jr2 SoCs.
> diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
> index 6910671..8038d54 100644
> --- a/drivers/pinctrl/mscc/Makefile
> +++ b/drivers/pinctrl/mscc/Makefile
> @@ -3,3 +3,4 @@
>  obj-y += mscc-common.o
>  obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
>  obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
> +obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
> diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c
> index d74b8a6..bd3e6ea 100644
> --- a/drivers/pinctrl/mscc/mscc-common.c
> +++ b/drivers/pinctrl/mscc/mscc-common.c
> @@ -22,16 +22,37 @@
>  #include <linux/io.h>
>  #include "mscc-common.h"
>  
> -#define MSCC_GPIO_OUT_SET	0x0
> -#define MSCC_GPIO_OUT_CLR	0x4
> -#define MSCC_GPIO_OUT		0x8
> -#define MSCC_GPIO_IN		0xc
> -#define MSCC_GPIO_OE		0x10
> -#define MSCC_GPIO_INTR		0x14
> -#define MSCC_GPIO_INTR_ENA	0x18
> -#define MSCC_GPIO_INTR_IDENT	0x1c
> -#define MSCC_GPIO_ALT0		0x20
> -#define MSCC_GPIO_ALT1		0x24
> +static void mscc_writel(unsigned int offset, void *addr)
> +{
> +	if (offset < 32)
> +		writel(BIT(offset), addr);
> +	else
> +		writel(BIT(offset % 32), addr + 4);
> +}
> +
> +static unsigned int mscc_readl(unsigned int offset, void *addr)
> +{
> +	if (offset < 32)
> +		return readl(addr);
> +	else
> +		return readl(addr + 4);
> +}
> +
> +static void mscc_setbits(unsigned int offset, void *addr)
> +{
> +	if (offset < 32)
> +		writel(readl(addr) | BIT(offset), addr);
> +	else
> +		writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
> +}
> +
> +static void mscc_clrbits(unsigned int offset, void *addr)
> +{
> +	if (offset < 32)
> +		writel(readl(addr) & ~BIT(offset), addr);
> +	else
> +		writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
> +}
>  
>  static int mscc_get_functions_count(struct udevice *dev)
>  {
> @@ -67,7 +88,7 @@ static int mscc_pinmux_set_mux(struct udevice *dev,
>  {
>  	struct mscc_pinctrl *info = dev_get_priv(dev);
>  	struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
> -	int f;
> +	int f, offset, regoff;
>  
>  	f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
>  	if (f < 0)
> @@ -79,15 +100,22 @@ static int mscc_pinmux_set_mux(struct udevice *dev,
>  	 * This is racy because both registers can't be updated at the same time
>  	 * but it doesn't matter much for now.
>  	 */
> +	offset = pin->pin;
> +	regoff = info->mscc_gpios[MSCC_GPIO_ALT0];
> +	if (offset >= 32) {
> +		offset = offset % 32;
> +		regoff = info->mscc_gpios[MSCC_GPIO_ALT1];
> +	}
> +
>  	if (f & BIT(0))
> -		setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
> +		mscc_setbits(offset, info->regs + regoff);
>  	else
> -		clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
> +		mscc_clrbits(offset, info->regs + regoff);
>  
>  	if (f & BIT(1))
> -		setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
> +		mscc_setbits(offset, info->regs + regoff + 4);
>  	else
> -		clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
> +		mscc_clrbits(offset, info->regs + regoff + 4);
>  
>  	return 0;
>  }
> @@ -120,8 +148,8 @@ static int mscc_create_group_func_map(struct udevice *dev,
>  		}
>  
>  		info->func[f].ngroups = npins;
> -		info->func[f].groups = devm_kzalloc(dev, npins *
> -						    sizeof(char *), GFP_KERNEL);
> +		info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
> +						    GFP_KERNEL);
>  		if (!info->func[f].groups)
>  			return -ENOMEM;
>  
> @@ -150,9 +178,15 @@ static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
>  	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
>  	unsigned int val;
>  
> -	val = readl(info->regs + MSCC_GPIO_IN);
> +	if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) &
> +	    BIT(offset % 32))
> +		val = mscc_readl(offset,
> +				 info->regs + info->mscc_gpios[MSCC_GPIO_OUT]);
> +	else
> +		val = mscc_readl(offset,
> +				 info->regs + info->mscc_gpios[MSCC_GPIO_IN]);
>  
> -	return !!(val & BIT(offset));
> +	return !!(val & BIT(offset % 32));
>  }
>  
>  static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
> @@ -160,9 +194,11 @@ static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
>  	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
>  
>  	if (value)
> -		writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
> +		mscc_writel(offset,
> +			    info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]);
>  	else
> -		writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
> +		mscc_writel(offset,
> +			    info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]);
>  
>  	return 0;
>  }
> @@ -172,16 +208,16 @@ static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
>  	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
>  	unsigned int val;
>  
> -	val = readl(info->regs + MSCC_GPIO_OE);
> +	val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
>  
> -	return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;
> +	return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;
>  }
>  
>  static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
>  {
>  	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
>  
> -	clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
> +	mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
>  
>  	return 0;
>  }
> @@ -191,7 +227,7 @@ static int mscc_gpio_direction_output(struct udevice *dev,
>  {
>  	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
>  
> -	setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
> +	mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
>  
>  	return mscc_gpio_set(dev, offset, value);
>  }
> @@ -215,7 +251,8 @@ const struct pinctrl_ops mscc_pinctrl_ops = {
>  
>  int mscc_pinctrl_probe(struct udevice *dev, int num_func,
>  		       const struct mscc_pin_data *mscc_pins, int num_pins,
> -		       char *const *function_names)
> +		       char * const *function_names,
> +		       const unsigned long *mscc_gpios)
>  {
>  	struct mscc_pinctrl *priv = dev_get_priv(dev);
>  	int ret;
> @@ -230,6 +267,7 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func,
>  	priv->mscc_pins = mscc_pins;
>  	priv->num_pins = num_pins;
>  	priv->function_names = function_names;
> +	priv->mscc_gpios = mscc_gpios;
>  	ret = mscc_pinctrl_register(dev, priv);
>  
>  	return ret;
> diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h
> index b0001db..3c5c1fa 100644
> --- a/drivers/pinctrl/mscc/mscc-common.h
> +++ b/drivers/pinctrl/mscc/mscc-common.h
> @@ -9,6 +9,19 @@
>  
>  #define MSCC_FUNC_PER_PIN	4
>  
> +enum mscc_regs_gpio {
> +	MSCC_GPIO_OUT_SET,
> +	MSCC_GPIO_OUT_CLR,
> +	MSCC_GPIO_OUT,
> +	MSCC_GPIO_IN,
> +	MSCC_GPIO_OE,
> +	MSCC_GPIO_INTR,
> +	MSCC_GPIO_INTR_ENA,
> +	MSCC_GPIO_INTR_IDENT,
> +	MSCC_GPIO_ALT0,
> +	MSCC_GPIO_ALT1,
> +};
> +
>  struct mscc_pin_caps {
>  	unsigned int pin;
>  	unsigned char functions[MSCC_FUNC_PER_PIN];
> @@ -41,11 +54,13 @@ struct mscc_pinctrl {
>  	const struct mscc_pin_data *mscc_pins;
>  	int num_pins;
>  	char * const *function_names;
> +	const unsigned long *mscc_gpios;
>  };
>  
>  int mscc_pinctrl_probe(struct udevice *dev, int num_func,
>  		       const struct mscc_pin_data *mscc_pins, int num_pins,
> -		       char * const *function_names);
> +		       char * const *function_names,
> +		       const unsigned long *mscc_gpios);
>  const struct pinctrl_ops mscc_pinctrl_ops;
>  
>  const struct dm_gpio_ops mscc_gpio_ops;
> diff --git a/drivers/pinctrl/mscc/pinctrl-jr2.c b/drivers/pinctrl/mscc/pinctrl-jr2.c
> new file mode 100644
> index 0000000..d4af76f
> --- /dev/null
> +++ b/drivers/pinctrl/mscc/pinctrl-jr2.c
> @@ -0,0 +1,323 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Microsemi SoCs pinctrl driver
> + *
> + * Author: <horatiu.vultur at microchip.com>
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include <common.h>
> +#include <config.h>
> +#include <dm.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +#include <dm/pinctrl.h>
> +#include <dm/root.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <linux/io.h>
> +#include <asm/gpio.h>
> +#include <asm/system.h>
> +#include "mscc-common.h"
> +
> +enum {
> +	FUNC_NONE,
> +	FUNC_GPIO,
> +	FUNC_IRQ0_IN,
> +	FUNC_IRQ0_OUT,
> +	FUNC_IRQ1_IN,
> +	FUNC_IRQ1_OUT,
> +	FUNC_MIIM1,
> +	FUNC_MIIM2,
> +	FUNC_PCI_WAKE,
> +	FUNC_PTP0,
> +	FUNC_PTP1,
> +	FUNC_PTP2,
> +	FUNC_PTP3,
> +	FUNC_PWM,
> +	FUNC_RECO_CLK0,
> +	FUNC_RECO_CLK1,
> +	FUNC_SFP0,
> +	FUNC_SFP1,
> +	FUNC_SFP2,
> +	FUNC_SFP3,
> +	FUNC_SFP4,
> +	FUNC_SFP5,
> +	FUNC_SFP6,
> +	FUNC_SFP7,
> +	FUNC_SFP8,
> +	FUNC_SFP9,
> +	FUNC_SFP10,
> +	FUNC_SFP11,
> +	FUNC_SFP12,
> +	FUNC_SFP13,
> +	FUNC_SFP14,
> +	FUNC_SFP15,
> +	FUNC_SG0,
> +	FUNC_SG1,
> +	FUNC_SG2,
> +	FUNC_SI,
> +	FUNC_TACHO,
> +	FUNC_TWI,
> +	FUNC_TWI2,
> +	FUNC_TWI_SCL_M,
> +	FUNC_UART,
> +	FUNC_UART2,
> +	FUNC_MAX
> +};
> +
> +char *jr2_function_names[] = {

should be: static const char *

> +	[FUNC_NONE]		= "none",
> +	[FUNC_GPIO]		= "gpio",
> +	[FUNC_IRQ0_IN]		= "irq0_in",
> +	[FUNC_IRQ0_OUT]		= "irq0_out",
> +	[FUNC_IRQ1_IN]		= "irq1_in",
> +	[FUNC_IRQ1_OUT]		= "irq1_out",
> +	[FUNC_MIIM1]		= "miim1",
> +	[FUNC_MIIM2]		= "miim2",
> +	[FUNC_PCI_WAKE]		= "pci_wake",
> +	[FUNC_PTP0]		= "ptp0",
> +	[FUNC_PTP1]		= "ptp1",
> +	[FUNC_PTP2]		= "ptp2",
> +	[FUNC_PTP3]		= "ptp3",
> +	[FUNC_PWM]		= "pwm",
> +	[FUNC_RECO_CLK0]	= "reco_clk0",
> +	[FUNC_RECO_CLK1]	= "reco_clk1",
> +	[FUNC_SFP0]		= "sfp0",
> +	[FUNC_SFP1]		= "sfp1",
> +	[FUNC_SFP2]		= "sfp2",
> +	[FUNC_SFP3]		= "sfp3",
> +	[FUNC_SFP4]		= "sfp4",
> +	[FUNC_SFP5]		= "sfp5",
> +	[FUNC_SFP6]		= "sfp6",
> +	[FUNC_SFP7]		= "sfp7",
> +	[FUNC_SFP8]		= "sfp8",
> +	[FUNC_SFP9]		= "sfp9",
> +	[FUNC_SFP10]		= "sfp10",
> +	[FUNC_SFP11]		= "sfp11",
> +	[FUNC_SFP12]		= "sfp12",
> +	[FUNC_SFP13]		= "sfp13",
> +	[FUNC_SFP14]		= "sfp14",
> +	[FUNC_SFP15]		= "sfp15",
> +	[FUNC_SG0]		= "sg0",
> +	[FUNC_SG1]		= "sg1",
> +	[FUNC_SG2]		= "sg2",
> +	[FUNC_SI]		= "si",
> +	[FUNC_TACHO]		= "tacho",
> +	[FUNC_TWI]		= "twi",
> +	[FUNC_TWI2]		= "twi2",
> +	[FUNC_TWI_SCL_M]	= "twi_scl_m",
> +	[FUNC_UART]		= "uart",
> +	[FUNC_UART2]		= "uart2",
> +};
> +
> +#define JR2_P(p, f0, f1)						\
> +static struct mscc_pin_caps jr2_pin_##p = {				\
> +	.pin = p,							\
> +	.functions = {							\
> +			FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE	\
> +	},								\
> +}
> +
> +JR2_P(0,  SG0,       NONE);
> +JR2_P(1,  SG0,       NONE);
> +JR2_P(2,  SG0,       NONE);
> +JR2_P(3,  SG0,       NONE);
> +JR2_P(4,  SG1,       NONE);
> +JR2_P(5,  SG1,       NONE);
> +JR2_P(6,  IRQ0_IN,   IRQ0_OUT);
> +JR2_P(7,  IRQ1_IN,   IRQ1_OUT);
> +JR2_P(8,  PTP0,      NONE);
> +JR2_P(9,  PTP1,      NONE);
> +JR2_P(10, UART,      NONE);
> +JR2_P(11, UART,      NONE);
> +JR2_P(12, SG1,       NONE);
> +JR2_P(13, SG1,       NONE);
> +JR2_P(14, TWI,       TWI_SCL_M);
> +JR2_P(15, TWI,       NONE);
> +JR2_P(16, SI,        TWI_SCL_M);
> +JR2_P(17, SI,        TWI_SCL_M);
> +JR2_P(18, SI,        TWI_SCL_M);
> +JR2_P(19, PCI_WAKE,  NONE);
> +JR2_P(20, IRQ0_OUT,  TWI_SCL_M);
> +JR2_P(21, IRQ1_OUT,  TWI_SCL_M);
> +JR2_P(22, TACHO,     NONE);
> +JR2_P(23, PWM,       NONE);
> +JR2_P(24, UART2,     NONE);
> +JR2_P(25, UART2,     SI);
> +JR2_P(26, PTP2,      SI);
> +JR2_P(27, PTP3,      SI);
> +JR2_P(28, TWI2,      SI);
> +JR2_P(29, TWI,       SI);
> +JR2_P(30, SG2,       SI);
> +JR2_P(31, SG2,       SI);
> +JR2_P(32, SG2,       SI);
> +JR2_P(33, SG2,       SI);
> +JR2_P(34, NONE,      TWI_SCL_M);
> +JR2_P(35, NONE,      TWI_SCL_M);
> +JR2_P(36, NONE,      TWI_SCL_M);
> +JR2_P(37, NONE,      TWI_SCL_M);
> +JR2_P(38, NONE,      TWI_SCL_M);
> +JR2_P(39, NONE,      TWI_SCL_M);
> +JR2_P(40, NONE,      TWI_SCL_M);
> +JR2_P(41, NONE,      TWI_SCL_M);
> +JR2_P(42, NONE,      TWI_SCL_M);
> +JR2_P(43, NONE,      TWI_SCL_M);
> +JR2_P(44, NONE,      SFP8);
> +JR2_P(45, NONE,      SFP9);
> +JR2_P(46, NONE,      SFP10);
> +JR2_P(47, NONE,      SFP11);
> +JR2_P(48, SFP0,      NONE);
> +JR2_P(49, SFP1,      SI);
> +JR2_P(50, SFP2,      SI);
> +JR2_P(51, SFP3,      SI);
> +JR2_P(52, SFP4,      NONE);
> +JR2_P(53, SFP5,      NONE);
> +JR2_P(54, SFP6,      NONE);
> +JR2_P(55, SFP7,      NONE);
> +JR2_P(56, MIIM1,     SFP12);
> +JR2_P(57, MIIM1,     SFP13);
> +JR2_P(58, MIIM2,     SFP14);
> +JR2_P(59, MIIM2,     SFP15);
> +JR2_P(60, NONE,      NONE);
> +JR2_P(61, NONE,      NONE);
> +JR2_P(62, NONE,      NONE);
> +JR2_P(63, NONE,      NONE);
> +
> +#define JR2_PIN(n) {						\
> +	.name = "GPIO_"#n,					\
> +	.drv_data = &jr2_pin_##n				\
> +}
> +
> +const struct mscc_pin_data jr2_pins[] = {

should be static

> +	JR2_PIN(0),
> +	JR2_PIN(1),
> +	JR2_PIN(2),
> +	JR2_PIN(3),
> +	JR2_PIN(4),
> +	JR2_PIN(5),
> +	JR2_PIN(6),
> +	JR2_PIN(7),
> +	JR2_PIN(8),
> +	JR2_PIN(9),
> +	JR2_PIN(10),
> +	JR2_PIN(11),
> +	JR2_PIN(12),
> +	JR2_PIN(13),
> +	JR2_PIN(14),
> +	JR2_PIN(15),
> +	JR2_PIN(16),
> +	JR2_PIN(17),
> +	JR2_PIN(18),
> +	JR2_PIN(19),
> +	JR2_PIN(20),
> +	JR2_PIN(21),
> +	JR2_PIN(22),
> +	JR2_PIN(23),
> +	JR2_PIN(24),
> +	JR2_PIN(25),
> +	JR2_PIN(26),
> +	JR2_PIN(27),
> +	JR2_PIN(28),
> +	JR2_PIN(29),
> +	JR2_PIN(30),
> +	JR2_PIN(31),
> +	JR2_PIN(32),
> +	JR2_PIN(33),
> +	JR2_PIN(34),
> +	JR2_PIN(35),
> +	JR2_PIN(36),
> +	JR2_PIN(37),
> +	JR2_PIN(38),
> +	JR2_PIN(39),
> +	JR2_PIN(40),
> +	JR2_PIN(41),
> +	JR2_PIN(42),
> +	JR2_PIN(43),
> +	JR2_PIN(44),
> +	JR2_PIN(45),
> +	JR2_PIN(46),
> +	JR2_PIN(47),
> +	JR2_PIN(48),
> +	JR2_PIN(49),
> +	JR2_PIN(50),
> +	JR2_PIN(51),
> +	JR2_PIN(52),
> +	JR2_PIN(53),
> +	JR2_PIN(54),
> +	JR2_PIN(55),
> +	JR2_PIN(56),
> +	JR2_PIN(57),
> +	JR2_PIN(58),
> +	JR2_PIN(59),
> +	JR2_PIN(60),
> +	JR2_PIN(61),
> +	JR2_PIN(62),
> +	JR2_PIN(63),
> +};
> +
> +const unsigned long jr2_gpios[] = {

should be static

> +	[MSCC_GPIO_OUT_SET] = 0x00,
> +	[MSCC_GPIO_OUT_CLR] = 0x08,
> +	[MSCC_GPIO_OUT] = 0x10,
> +	[MSCC_GPIO_IN] = 0x18,
> +	[MSCC_GPIO_OE] = 0x20,
> +	[MSCC_GPIO_INTR] = 0x28,
> +	[MSCC_GPIO_INTR_ENA] = 0x30,
> +	[MSCC_GPIO_INTR_IDENT] = 0x38,
> +	[MSCC_GPIO_ALT0] = 0x40,
> +	[MSCC_GPIO_ALT1] = 0x48,
> +};
> +
> +static int jr2_gpio_probe(struct udevice *dev)
> +{
> +	struct gpio_dev_priv *uc_priv;
> +
> +	uc_priv = dev_get_uclass_priv(dev);
> +	uc_priv->bank_name = "jr2-gpio";
> +	uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
> +
> +	return 0;
> +}
> +
> +static struct driver jr2_gpio_driver = {
> +	.name	= "jr2-gpio",
> +	.id	= UCLASS_GPIO,
> +	.probe	= jr2_gpio_probe,
> +	.ops	= &mscc_gpio_ops,
> +};
> +
> +int jr2_pinctrl_probe(struct udevice *dev)

should be static

> +{
> +	int ret;
> +
> +	ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
> +				 ARRAY_SIZE(jr2_pins),
> +				 jr2_function_names,
> +				 jr2_gpios);
> +
> +	if (ret)
> +		return ret;
> +
> +	ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
> +			  dev_of_offset(dev), NULL);
> +
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static const struct udevice_id jr2_pinctrl_of_match[] = {
> +	{ .compatible = "mscc,jaguar2-pinctrl" },
> +	{},
> +};
> +
> +U_BOOT_DRIVER(jr2_pinctrl) = {
> +	.name = "jr2-pinctrl",
> +	.id = UCLASS_PINCTRL,
> +	.of_match = of_match_ptr(jr2_pinctrl_of_match),
> +	.probe = jr2_pinctrl_probe,
> +	.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
> +	.ops = &mscc_pinctrl_ops,
> +};
> diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c b/drivers/pinctrl/mscc/pinctrl-luton.c
> index 7166588..8c636ff 100644
> --- a/drivers/pinctrl/mscc/pinctrl-luton.c
> +++ b/drivers/pinctrl/mscc/pinctrl-luton.c
> @@ -123,6 +123,19 @@ static const struct mscc_pin_data luton_pins[] = {
>  	LUTON_PIN(31),
>  };
>  
> +const unsigned long luton_gpios[] = {

should be static

> +	[MSCC_GPIO_OUT_SET] = 0x00,
> +	[MSCC_GPIO_OUT_CLR] = 0x04,
> +	[MSCC_GPIO_OUT] = 0x08,
> +	[MSCC_GPIO_IN] = 0x0c,
> +	[MSCC_GPIO_OE] = 0x10,
> +	[MSCC_GPIO_INTR] = 0x14,
> +	[MSCC_GPIO_INTR_ENA] = 0x18,
> +	[MSCC_GPIO_INTR_IDENT] = 0x1c,
> +	[MSCC_GPIO_ALT0] = 0x20,
> +	[MSCC_GPIO_ALT1] = 0x24,
> +};
> +
>  static int luton_gpio_probe(struct udevice *dev)
>  {
>  	struct gpio_dev_priv *uc_priv;
> @@ -146,7 +159,8 @@ int luton_pinctrl_probe(struct udevice *dev)
>  	int ret;
>  
>  	ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
> -				 ARRAY_SIZE(luton_pins), luton_function_names);
> +				 ARRAY_SIZE(luton_pins), luton_function_names,
> +				 luton_gpios);
>  
>  	if (ret)
>  		return ret;
> diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c b/drivers/pinctrl/mscc/pinctrl-ocelot.c
> index 10f9b90..fb02061 100644
> --- a/drivers/pinctrl/mscc/pinctrl-ocelot.c
> +++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c
> @@ -138,6 +138,19 @@ static const struct mscc_pin_data ocelot_pins[] = {
>  	OCELOT_PIN(21),
>  };
>  
> +const unsigned long ocelot_gpios[] = {

should be static

> +	[MSCC_GPIO_OUT_SET] = 0x00,
> +	[MSCC_GPIO_OUT_CLR] = 0x04,
> +	[MSCC_GPIO_OUT] = 0x08,
> +	[MSCC_GPIO_IN] = 0x0c,
> +	[MSCC_GPIO_OE] = 0x10,
> +	[MSCC_GPIO_INTR] = 0x14,
> +	[MSCC_GPIO_INTR_ENA] = 0x18,
> +	[MSCC_GPIO_INTR_IDENT] = 0x1c,
> +	[MSCC_GPIO_ALT0] = 0x20,
> +	[MSCC_GPIO_ALT1] = 0x24,
> +};
> +
>  static int ocelot_gpio_probe(struct udevice *dev)
>  {
>  	struct gpio_dev_priv *uc_priv;
> @@ -162,7 +175,8 @@ int ocelot_pinctrl_probe(struct udevice *dev)
>  
>  	ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
>  				 ARRAY_SIZE(ocelot_pins),
> -				 ocelot_function_names);
> +				 ocelot_function_names,
> +				 ocelot_gpios);
>  
>  	if (ret)
>  		return ret;
> 

-- 
- Daniel


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