[U-Boot] [PATCH 8/8] Add support for the NXP LS1021A-TSN board

Joe Hershberger joe.hershberger at ni.com
Mon Jul 15 19:09:09 UTC 2019


On Sun, Jun 23, 2019 at 12:53 PM Vladimir Oltean <olteanv at gmail.com> wrote:
>
> From: Jianchao Wang <jianchao.wang at nxp.com>
>
> The LS1021A-TSN is a development board built by VVDN/Argonboards in
> partnership with NXP.
>
> It features the LS1021A SoC and the first-generation SJA1105T Ethernet
> switch for prototyping implementations of a subset of IEEE 802.1 TSN
> standards.
>
> Supported boot media: microSD card (via SPL), QSPI flash.
>
> Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which
> is 64 MB in size and has an erase sector size of 256KB (therefore,
> flashing the RCW would erase part of U-boot).
>
> Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which
> is only 32 MB in size but has an erase sector size of 64KB (therefore
> the RCW image can be flashed without erasing U-boot).
>
> To avoid the problems above, the U-boot base address has been selected
> at 0x100000 (the start of the 5th 256KB erase sector), which works for
> all board revisions. Actually 0x40000 would have been enough, but
> 0x100000 is common for all Layerscape devices.
>
> eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but
> SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is
> disabled.
>
> Signed-off-by: Xiaoliang Yang <xiaoliang.yang at nxp.com>
> Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> Signed-off-by: Jianchao Wang <jianchao.wang at nxp.com>
> Signed-off-by: Changming Huang <jerry.huang at nxp.com>
>
> [Vladimir] Code taken from https://github.com/openil/u-boot (which
> itself is mostly copied from ls1021a-iot) and adapted with the following
> changes:
>
> - Add a008850 errata workaround
> - Converted eTSEC, MMC to DM to avoid all build warnings
> - Plugged in distro boot feature, including support for extlinux.conf
> - Added defconfig for QSPI boot
> - Added the board/freescale/ls1021atsn/README.rst for initial setup
>
> Signed-off-by: Vladimir Oltean <olteanv at gmail.com>
> ---
>  arch/arm/Kconfig                              |  14 +
>  arch/arm/dts/Makefile                         |   2 +-
>  arch/arm/dts/ls1021a-tsn.dts                  |  77 ++++
>  board/freescale/ls1021atsn/Kconfig            |  18 +
>  board/freescale/ls1021atsn/MAINTAINERS        |   8 +
>  board/freescale/ls1021atsn/Makefile           |   3 +
>  board/freescale/ls1021atsn/README.rst         |  96 +++++
>  board/freescale/ls1021atsn/ls1021atsn.c       | 291 +++++++++++++++
>  board/freescale/ls1021atsn/ls102xa_pbi.cfg    |  15 +
>  board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg |   8 +
>  configs/ls1021atsn_qspi_defconfig             |  76 ++++
>  configs/ls1021atsn_sdcard_defconfig           |  85 +++++
>  include/configs/ls1021atsn.h                  | 346 ++++++++++++++++++
>  13 files changed, 1038 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/ls1021a-tsn.dts
>  create mode 100644 board/freescale/ls1021atsn/Kconfig
>  create mode 100644 board/freescale/ls1021atsn/MAINTAINERS
>  create mode 100644 board/freescale/ls1021atsn/Makefile
>  create mode 100644 board/freescale/ls1021atsn/README.rst
>  create mode 100644 board/freescale/ls1021atsn/ls1021atsn.c
>  create mode 100644 board/freescale/ls1021atsn/ls102xa_pbi.cfg
>  create mode 100644 board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
>  create mode 100644 configs/ls1021atsn_qspi_defconfig
>  create mode 100644 configs/ls1021atsn_sdcard_defconfig
>  create mode 100644 include/configs/ls1021atsn.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 01ff57cf1bec..5edac7ea2bd5 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1327,6 +1327,19 @@ config TARGET_LS1021ATWR
>         select SUPPORT_SPL
>         imply SCSI
>
> +config TARGET_LS1021ATSN
> +       bool "Support ls1021atsn"
> +       select ARCH_LS1021A
> +       select ARCH_SUPPORT_PSCI
> +       select BOARD_EARLY_INIT_F
> +       select BOARD_LATE_INIT
> +       select CPU_V7A
> +       select CPU_V7_HAS_NONSEC
> +       select CPU_V7_HAS_VIRT
> +       select LS1_DEEP_SLEEP
> +       select SUPPORT_SPL
> +       imply SCSI
> +
>  config TARGET_LS1021AIOT
>         bool "Support ls1021aiot"
>         select ARCH_LS1021A
> @@ -1693,6 +1706,7 @@ source "board/freescale/ls1028a/Kconfig"
>  source "board/freescale/ls1021aqds/Kconfig"
>  source "board/freescale/ls1043aqds/Kconfig"
>  source "board/freescale/ls1021atwr/Kconfig"
> +source "board/freescale/ls1021atsn/Kconfig"
>  source "board/freescale/ls1021aiot/Kconfig"
>  source "board/freescale/ls1046aqds/Kconfig"
>  source "board/freescale/ls1043ardb/Kconfig"
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 528fb909d5b0..28590b0c5530 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -325,7 +325,7 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
>  dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
>         ls1021a-qds-lpuart.dtb \
>         ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
> -       ls1021a-iot-duart.dtb
> +       ls1021a-iot-duart.dtb ls1021a-tsn.dtb
>  dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
>         fsl-ls2080a-rdb.dtb \
>         fsl-ls2081a-rdb.dtb \
> diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts
> new file mode 100644
> index 000000000000..f633074099dc
> --- /dev/null
> +++ b/arch/arm/dts/ls1021a-tsn.dts
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2016-2018 NXP Semiconductors
> + * Copyright 2019 Vladimir Oltean <olteanv at gmail.com>
> + */
> +
> +/dts-v1/;
> +#include "ls1021a.dtsi"
> +
> +/ {
> +       model = "NXP LS1021A-TSN Board";
> +
> +       aliases {
> +               enet0-sgmii-phy = &sgmii_phy2;
> +               enet1-sgmii-phy = &sgmii_phy1;
> +               spi0 = &qspi;
> +               spi1 = &dspi1;
> +       };
> +};
> +
> +&enet0 {
> +       tbi-handle = <&tbi0>;
> +       phy-handle = <&sgmii_phy2>;
> +       phy-mode = "sgmii";
> +       status = "okay";
> +};
> +
> +&enet1 {
> +       tbi-handle = <&tbi1>;
> +       phy-handle = <&sgmii_phy1>;
> +       phy-mode = "sgmii";
> +       status = "okay";
> +};
> +
> +&i2c0 {
> +       status = "okay";
> +};
> +
> +&mdio0 {
> +       /* AR8031 */
> +       sgmii_phy1: ethernet-phy at 1 {
> +               reg = <0x1>;
> +       };
> +
> +       /* AR8031 */
> +       sgmii_phy2: ethernet-phy at 2 {
> +               reg = <0x2>;
> +       };
> +
> +       /* SGMII PCS for enet0 */
> +       tbi0: tbi-phy at 1f {
> +               reg = <0x1f>;
> +               device_type = "tbi-phy";
> +       };
> +};
> +
> +&mdio1 {
> +       /* SGMII PCS for enet1 */
> +       tbi1: tbi-phy at 1f {
> +               reg = <0x1f>;
> +               device_type = "tbi-phy";
> +       };
> +};
> +
> +&qspi {
> +       bus-num = <0>;
> +       status = "okay";
> +
> +       flash at 0 {
> +               compatible = "spi-flash";
> +               spi-max-frequency = <20000000>;
> +               reg = <0>;
> +       };
> +};
> +
> +&uart0 {
> +       status = "okay";
> +};
> diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig
> new file mode 100644
> index 000000000000..d999fa469002
> --- /dev/null
> +++ b/board/freescale/ls1021atsn/Kconfig
> @@ -0,0 +1,18 @@
> +# SPDX-License-Identifier: GPL-2.0
> +if TARGET_LS1021ATSN
> +
> +config SYS_BOARD
> +       default "ls1021atsn"
> +
> +config SYS_VENDOR
> +       default "freescale"
> +
> +config SYS_SOC
> +       default "ls102xa"
> +
> +config SYS_CONFIG_NAME
> +       default "ls1021atsn"
> +
> +source "board/freescale/common/Kconfig"
> +
> +endif
> diff --git a/board/freescale/ls1021atsn/MAINTAINERS b/board/freescale/ls1021atsn/MAINTAINERS
> new file mode 100644
> index 000000000000..560bb615d2fe
> --- /dev/null
> +++ b/board/freescale/ls1021atsn/MAINTAINERS
> @@ -0,0 +1,8 @@
> +NXP LS1021A-TSN Board
> +M:     Vladimir Oltean <olteanv at gmail.com>
> +S:     Maintained
> +F:     arch/arm/dts/ls1021a-tsn.dts
> +F:     board/freescale/ls1021atsn/
> +F:     include/configs/ls1021atsn.h
> +F:     configs/ls1021atsn_qspi_defconfig
> +F:     configs/ls1021atsn_sdcard_defconfig
> diff --git a/board/freescale/ls1021atsn/Makefile b/board/freescale/ls1021atsn/Makefile
> new file mode 100644
> index 000000000000..b4808f05e8e0
> --- /dev/null
> +++ b/board/freescale/ls1021atsn/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +obj-y += ls1021atsn.o
> +obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o
> diff --git a/board/freescale/ls1021atsn/README.rst b/board/freescale/ls1021atsn/README.rst
> new file mode 100644
> index 000000000000..e986f460c4d4
> --- /dev/null
> +++ b/board/freescale/ls1021atsn/README.rst
> @@ -0,0 +1,96 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +LS1021A-TSN Board Overview
> +==========================
> +
> + - 1GB DDR3 at 800 MHz
> + - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash
> + - Ethernet
> +     - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031)
> +     - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R)
> +     - One internal RGMII port connected to the switch
> + - SDHC
> +     - microSDHC/SDXC connector
> + - Other I/O
> +    - One Serial port
> +    - Arduino and expansion headers
> +    - mPCIE slot
> +    - SATA port
> +    - USB3.0 port
> +
> +LS1021A Memory map
> +==================
> +
> +The addresses in brackets are physical addresses.
> +
> +==============  ==============  ==============================  =======
> +Start Address   End Address     Description                     Size
> +==============  ==============  ==============================  =======
> +0x00_0000_0000  0x00_000F_FFFF  Secure Boot ROM                 1MB
> +0x00_0100_0000  0x00_0FFF_FFFF  CCSRBAR                         240MB
> +0x00_1000_0000  0x00_1000_FFFF  OCRAM0                          64KB
> +0x00_1001_0000  0x00_1001_FFFF  OCRAM1                          64KB
> +0x00_2000_0000  0x00_20FF_FFFF  DCSR                            16MB
> +0x00_4000_0000  0x00_5FFF_FFFF  QSPI                            512MB
> +0x00_6000_0000  0x00_67FF_FFFF  IFC - NOR Flash                 128MB
> +0x00_8000_0000  0x00_FFFF_FFFF  DRAM1                           2GB
> +==============  ==============  ==============================  =======
> +
> +Compiling and flashing
> +======================
> +
> +The LS1021A-TSN board comes along with a microSD card with OpenIL U-boot.
> +That will be used to update the internal QSPI flash, as well as
> +
> +To compile and flash an SD card image::
> +
> +  make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/
> +  => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100
> +
> +For the QSPI flash, first obtain the Reset Configuration Word binary for
> +bootimg from the QSPI flash from the rcw project
> +(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw)::
> +
> +  make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/
> +
> +The above RCW binary takes care of swapping the QSPI AMBA memory, so that the
> +U-boot binary does not need to be swapped when flashing it.
> +
> +To compile and flash a U-boot image for QSPI::
> +
> +  make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/
> +
> +Then optionally create a custom uboot-env.txt file (although the default
> +environment already supports distro boot) and convert it to binary format::
> +
> +  mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt
> +
> +To program the QSPI flash with the images::
> +
> +  => tftp 0x82000000 rcw_1000_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize}
> +  => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize}
> +  => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize}
> +
> +The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC
> +addresses of the Ethernet interfaces, however the EEPROM comes blank out of
> +the factory, and the MAC addresses are printed on a label on the bottom of
> +the boards.
> +
> +To write the MAC addresses to the EEPROM, the following needs to be done once::
> +
> +  => mac id
> +  => mac 0 00:1F:7B:xx:xx:xx
> +  => mac 1 00:1F:7B:xx:xx:xx
> +  => mac 2 00:1F:7B:xx:xx:xx
> +  => mac save
> +
> +The switch ports do not have their own MAC address - they inherit it from the
> +master enet2 port.
> +
> +Known issues and limitations
> +============================
> +
> +- The 4 SJA1105 switch ports are not functional in U-boot for now.
> +- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is
> +  no way to talk to the CPLD for e.g. running the "qixis_reset" command, or
> +  turning the fan on, etc.
> diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
> new file mode 100644
> index 000000000000..84c2af142956
> --- /dev/null
> +++ b/board/freescale/ls1021atsn/ls1021atsn.c
> @@ -0,0 +1,291 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2016-2019 NXP Semiconductors
> + */
> +#include <common.h>
> +#include <i2c.h>
> +#include <asm/io.h>
> +#include <asm/arch/immap_ls102xa.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/fsl_serdes.h>
> +#include <asm/arch-ls102xa/ls102xa_soc.h>
> +#include <asm/arch/ls102xa_devdis.h>
> +#include <asm/arch/ls102xa_soc.h>
> +#include <hwconfig.h>
> +#include <mmc.h>
> +#include <fsl_csu.h>
> +#include <fsl_esdhc.h>
> +#include <fsl_ifc.h>
> +#include <fsl_immap.h>
> +#include <netdev.h>
> +#include <spl.h>
> +#include "../common/sleep.h"
> +#ifdef CONFIG_U_QE
> +#include <fsl_qe.h>
> +#endif
> +#include <fsl_validate.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void cpld_show(void)
> +{
> +       struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
> +       u32 cpldrev;
> +       int major;
> +       int minor;
> +
> +       cpldrev = in_be32(&dcfg->gpporcr1);
> +       major = (cpldrev >> 28) & 0xf;
> +       minor = (cpldrev >> 24) & 0xf;
> +
> +       printf("CPLD:  V%d.%d\n", major, minor);
> +}
> +
> +int checkboard(void)
> +{
> +       puts("Board: LS1021ATSN\n");
> +       cpld_show();
> +       return 0;
> +}
> +
> +void ddrmc_init(void)
> +{
> +       struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
> +       u32 temp_sdram_cfg, tmp;
> +
> +       out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
> +
> +       out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
> +       out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
> +
> +       out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
> +       out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
> +       out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
> +       out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
> +       out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
> +       out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
> +
> +#ifdef CONFIG_DEEP_SLEEP
> +       if (is_warm_boot()) {
> +               out_be32(&ddr->sdram_cfg_2,
> +                        DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
> +               out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
> +               out_be32(&ddr->init_ext_addr, (1 << 31));
> +
> +               /* DRAM VRef will not be trained */
> +               out_be32(&ddr->ddr_cdr2,
> +                        DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
> +       } else
> +#endif
> +       {
> +               out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
> +               out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
> +       }
> +
> +       out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
> +       out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
> +
> +       out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
> +
> +       out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
> +
> +       out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
> +       out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
> +
> +       out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
> +
> +       out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
> +       out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
> +
> +       out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
> +
> +       /* DDR erratum A-009942 */
> +       tmp = in_be32(&ddr->debug[28]);
> +       out_be32(&ddr->debug[28], tmp | 0x0070006f);
> +
> +       udelay(1);
> +
> +#ifdef CONFIG_DEEP_SLEEP
> +       if (is_warm_boot()) {
> +               /* enter self-refresh */
> +               temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
> +               temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
> +               out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
> +
> +               temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
> +       } else
> +#endif
> +               temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
> +
> +       out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
> +
> +#ifdef CONFIG_DEEP_SLEEP
> +       if (is_warm_boot()) {
> +               /* exit self-refresh */
> +               temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
> +               temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
> +               out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
> +       }
> +#endif
> +}
> +
> +int dram_init(void)
> +{
> +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
> +       ddrmc_init();
> +#endif
> +
> +       erratum_a008850_post();
> +
> +       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> +
> +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
> +       fsl_dp_resume();
> +#endif
> +
> +       return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +       return pci_eth_init(bis);
> +}
> +
> +int board_early_init_f(void)
> +{
> +       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
> +
> +#ifdef CONFIG_TSEC_ENET
> +       /* Clear BD & FR bits for big endian BD's and frame data (aka set

Nit: Multi-line comment format.  I'm curious why checkpatch.pl doesn't
catch this sometimes.

> +        * correct eTSEC endianness). This is crucial in ensuring that it does
> +        * not report Data Parity Errors in its RX/TX FIFOs when attempting to
> +        * send traffic.
> +        */
> +       clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> +       /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
> +       out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
> +#endif
> +
> +#ifdef CONFIG_FSL_IFC
> +       init_early_memctl_regs();
> +#endif
> +
> +       arch_soc_init();
> +
> +#if defined(CONFIG_DEEP_SLEEP)
> +       if (is_warm_boot()) {
> +               timer_init();
> +               dram_init();
> +       }
> +#endif
> +
> +       return 0;
> +}
> +
> +#ifdef CONFIG_SPL_BUILD
> +void board_init_f(ulong dummy)
> +{
> +       void (*second_uboot)(void);
> +
> +       /* Clear the BSS */
> +       memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +       get_clocks();
> +
> +#if defined(CONFIG_DEEP_SLEEP)
> +       if (is_warm_boot())
> +               fsl_dp_disable_console();
> +#endif
> +
> +       preloader_console_init();
> +
> +       dram_init();
> +
> +       /* Allow OCRAM access permission as R/W */
> +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> +       enable_layerscape_ns_access();
> +       enable_layerscape_ns_access();
> +#endif
> +
> +       /*
> +        * if it is woken up from deep sleep, then jump to second
> +        * stage uboot and continue executing without recopying

U-Boot

> +        * it from SD since it has already been reserved in memory
> +        * in last boot.
> +        */
> +       if (is_warm_boot()) {
> +               second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
> +               second_uboot();
> +       }
> +
> +       board_init_r(NULL, 0);
> +}
> +#endif
> +
> +int board_init(void)
> +{
> +#ifndef CONFIG_SYS_FSL_NO_SERDES
> +       fsl_serdes_init();
> +#endif
> +       ls102xa_smmu_stream_id_init();
> +
> +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> +       enable_layerscape_ns_access();
> +#endif
> +
> +#ifdef CONFIG_U_QE
> +       u_qe_init();
> +#endif
> +
> +       return 0;
> +}
> +
> +#if defined(CONFIG_SPL_BUILD)
> +void spl_board_init(void)
> +{
> +       ls102xa_smmu_stream_id_init();
> +}
> +#endif
> +
> +#ifdef CONFIG_BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_CHAIN_OF_TRUST
> +       fsl_setenv_chain_of_trust();
> +#endif
> +
> +       return 0;
> +}
> +#endif
> +
> +#if defined(CONFIG_MISC_INIT_R)
> +int misc_init_r(void)
> +{
> +#ifdef CONFIG_FSL_DEVICE_DISABLE
> +       device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
> +#endif
> +
> +#ifdef CONFIG_FSL_CAAM
> +       return sec_init();
> +#endif
> +}
> +#endif
> +
> +#if defined(CONFIG_DEEP_SLEEP)
> +void board_sleep_prepare(void)
> +{
> +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> +       enable_layerscape_ns_access();
> +#endif
> +}
> +#endif
> +
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> +       ft_cpu_setup(blob, bd);
> +
> +#ifdef CONFIG_PCI
> +       ft_pci_setup(blob, bd);
> +#endif
> +
> +       return 0;
> +}
> diff --git a/board/freescale/ls1021atsn/ls102xa_pbi.cfg b/board/freescale/ls1021atsn/ls102xa_pbi.cfg
> new file mode 100644
> index 000000000000..a8ba184c6684
> --- /dev/null
> +++ b/board/freescale/ls1021atsn/ls102xa_pbi.cfg

What is this file? Is it built by something?

> @@ -0,0 +1,15 @@
> +#PBI commands
> +
> +09570200 ffffffff
> +09570158 00000300
> +8940007c 21f47300
> +
> +# Configure Scratch register
> +09ee0200 10000000
> +# Configure alternate space
> +09570158 00001000
> +# Flush PBL data
> +096100c0 000FFFFF
> +
> +09ea085c 00502880
> +09ea0560 80800000
> diff --git a/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
> new file mode 100644
> index 000000000000..67152dd2810e
> --- /dev/null
> +++ b/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
> @@ -0,0 +1,8 @@
> +# PBL preamble and RCW header
> +aa55aa55 01ee0100
> +
> +# Disable IFC, enable QSPI and DSPI
> +0608000c 00000000 00000000 00000000
> +30000000 08007900 60040a00 21046000
> +00000000 00000000 00000000 20002000
> +20024800 8804b340 00000000 00000000
> diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
> new file mode 100644
> index 000000000000..427881fe0c52
> --- /dev/null
> +++ b/configs/ls1021atsn_qspi_defconfig
> @@ -0,0 +1,76 @@
> +CONFIG_ARM=y
> +CONFIG_TARGET_LS1021ATSN=y
> +CONFIG_SYS_TEXT_BASE=0x40100000
> +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SYS_FSL_CLK=y
> +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
> +CONFIG_QSPI_BOOT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_GREPENV=y
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_FAT=y
> +CONFIG_FSL_ESDHC=y
> +CONFIG_CMD_SF=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_DM=y
> +CONFIG_FSL_CAAM=y
> +CONFIG_SPI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_ATMEL=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_NETDEVICES=y
> +CONFIG_DM_ETH=y
> +CONFIG_TSEC_ENET=y
> +CONFIG_MII=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_DM_SPI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH_DATAFLASH=y
> +CONFIG_FSL_DSPI=y
> +CONFIG_FSL_QSPI=y
> +CONFIG_PCI=y
> +CONFIG_CMD_PCI=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_CMD_MMC=y
> +CONFIG_DM_MMC=y
> +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_CMD_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_FSL=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_HAS_FSL_XHCI_USB=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_PCIE_LAYERSCAPE=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_PHY_BROADCOM=y
> +CONFIG_PHY_FIXED=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMDLINE_TAG=y
> +CONFIG_CMDLINE_EDITING=y
> +CONFIG_AUTO_COMPLETE=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_SYS_LONGHELP=y
> +CONFIG_FIT=y
> +CONFIG_CMD_DM=y
> +CONFIG_AHCI=y
> +CONFIG_CMD_I2C=y
> +CONFIG_BLK=y
> +CONFIG_CMD_PART=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_CMD_FS_UUID=y
> +CONFIG_DISTRO_DEFAULTS=y
> diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
> new file mode 100644
> index 000000000000..b74e01206817
> --- /dev/null
> +++ b/configs/ls1021atsn_sdcard_defconfig
> @@ -0,0 +1,85 @@
> +CONFIG_ARM=y
> +CONFIG_TARGET_LS1021ATSN=y
> +CONFIG_SPL_TEXT_BASE=0x10000000
> +CONFIG_SYS_TEXT_BASE=0x82000000
> +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SPL=y
> +CONFIG_SPL_FRAMEWORK=y
> +CONFIG_SYS_FSL_CLK=y
> +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
> +CONFIG_SD_BOOT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_GREPENV=y
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_MMC=y
> +CONFIG_FSL_ESDHC=y
> +CONFIG_CMD_SF=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_DM=y
> +CONFIG_FSL_CAAM=y
> +CONFIG_SPI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_ATMEL=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_NETDEVICES=y
> +CONFIG_DM_ETH=y
> +CONFIG_TSEC_ENET=y
> +CONFIG_MII=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_DM_SPI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH_DATAFLASH=y
> +CONFIG_FSL_DSPI=y
> +CONFIG_FSL_QSPI=y
> +CONFIG_PCI=y
> +CONFIG_CMD_PCI=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_CMD_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_FSL=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_HAS_FSL_XHCI_USB=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_PCIE_LAYERSCAPE=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_PHY_BROADCOM=y
> +CONFIG_PHY_FIXED=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMDLINE_TAG=y
> +CONFIG_CMDLINE_EDITING=y
> +CONFIG_AUTO_COMPLETE=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_SYS_LONGHELP=y
> +CONFIG_FIT=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_ENV_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_CMD_DM=y
> +CONFIG_AHCI=y
> +CONFIG_CMD_I2C=y
> +CONFIG_BLK=y
> +CONFIG_DM_MMC=y
> +CONFIG_CMD_PART=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_CMD_FS_UUID=y
> +CONFIG_DISTRO_DEFAULTS=y
> diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
> new file mode 100644
> index 000000000000..c8ec414afd39
> --- /dev/null
> +++ b/include/configs/ls1021atsn.h
> @@ -0,0 +1,346 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + * Copyright 2016-2018 NXP Semiconductors
> + * Copyright 2019 Vladimir Oltean <olteanv at gmail.com>
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR
> +
> +#define CONFIG_SYS_FSL_CLK
> +
> +#define CONFIG_DEEP_SLEEP
> +#ifdef CONFIG_DEEP_SLEEP
> +#define CONFIG_SILENT_CONSOLE
> +#endif
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
> +
> +/* XHCI Support - enabled by default */
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
> +
> +#define CONFIG_SYS_CLK_FREQ            100000000
> +#define CONFIG_DDR_CLK_FREQ            100000000
> +
> +#define DDR_SDRAM_CFG                  0x470c0008
> +#define DDR_CS0_BNDS                   0x008000bf
> +#define DDR_CS0_CONFIG                 0x80014302
> +#define DDR_TIMING_CFG_0               0x50550004
> +#define DDR_TIMING_CFG_1               0xbcb38c56
> +#define DDR_TIMING_CFG_2               0x0040d120
> +#define DDR_TIMING_CFG_3               0x010e1000
> +#define DDR_TIMING_CFG_4               0x00000001
> +#define DDR_TIMING_CFG_5               0x03401400
> +#define DDR_SDRAM_CFG_2                        0x00401010
> +#define DDR_SDRAM_MODE                 0x00061c60
> +#define DDR_SDRAM_MODE_2               0x00180000
> +#define DDR_SDRAM_INTERVAL             0x18600618
> +#define DDR_DDR_WRLVL_CNTL             0x8655f605
> +#define DDR_DDR_WRLVL_CNTL_2           0x05060607
> +#define DDR_DDR_WRLVL_CNTL_3           0x05050505
> +#define DDR_DDR_CDR1                   0x80040000
> +#define DDR_DDR_CDR2                   0x00000001
> +#define DDR_SDRAM_CLK_CNTL             0x02000000
> +#define DDR_DDR_ZQ_CNTL                        0x89080600
> +#define DDR_CS0_CONFIG_2               0
> +#define DDR_SDRAM_CFG_MEM_EN           0x80000000
> +#define SDRAM_CFG2_D_INIT              0x00000010
> +#define DDR_CDR2_VREF_TRAIN_EN         0x00000080
> +#define SDRAM_CFG2_FRC_SR              0x80000000
> +#define SDRAM_CFG_BI                   0x00000001
> +
> +#define CONFIG_CHIP_SELECTS_PER_CTRL   4
> +
> +#ifdef CONFIG_RAMBOOT_PBL
> +#define CONFIG_SYS_FSL_PBL_PBI \
> +       "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
> +#endif
> +
> +#ifdef CONFIG_SD_BOOT
> +#ifdef CONFIG_SD_BOOT_QSPI
> +#define CONFIG_SYS_FSL_PBL_RCW \
> +       "board/freescale/ls1021atsn/ls102xa_rcw_sd_qspi.cfg"
> +#else
> +#define CONFIG_SYS_FSL_PBL_RCW \
> +       "board/freescale/ls1021atsn/ls102xa_rcw_sd_ifc.cfg"
> +#endif
> +#define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0xe8
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#define CONFIG_U_BOOT_HDR_SIZE         (16 << 10)
> +#endif /* ifdef CONFIG_SECURE_BOOT */
> +
> +#define CONFIG_SPL_MAX_SIZE            0x1a000
> +#define CONFIG_SPL_STACK               0x1001d000
> +#define CONFIG_SPL_PAD_TO              0x1c000
> +
> +#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SYS_TEXT_BASE + \
> +               CONFIG_SYS_MONITOR_LEN)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
> +#define CONFIG_SPL_BSS_START_ADDR      0x80100000
> +#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
> +
> +#ifdef CONFIG_U_BOOT_HDR_SIZE
> +/*
> + * HDR would be appended at end of image and copied to DDR along
> + * with U-Boot image. Here u-boot max. size is 512K. So if binary

U-Boot (second one).

> + * size increases then increase this size in case of secure boot as
> + * it uses raw u-boot image instead of fit image.

U-Boot

> + */
> +#define CONFIG_SYS_MONITOR_LEN         (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
> +#else
> +#define CONFIG_SYS_MONITOR_LEN         0x80000
> +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
> +#endif
> +
> +#define CONFIG_NR_DRAM_BANKS           1
> +#define PHYS_SDRAM                     0x80000000
> +#define PHYS_SDRAM_SIZE                        (1u * 1024 * 1024 * 1024)
> +
> +#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
> +#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
> +
> +#define CONFIG_CHIP_SELECTS_PER_CTRL   4
> +
> +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
> +       !defined(CONFIG_QSPI_BOOT)
> +#define CONFIG_U_QE
> +#endif
> +
> +/*
> + * IFC Definitions
> + */
> +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
> +#define CONFIG_FSL_IFC
> +#endif
> +
> +/* CPLD */
> +#define CONFIG_SYS_CPLD_BASE           0x7fb00000
> +#define CPLD_BASE_PHYS                 CONFIG_SYS_CPLD_BASE
> +
> +#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
> +#define CONFIG_SYS_FPGA_CSPR           (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
> +                                       CSPR_PORT_SIZE_8 | \
> +                                       CSPR_MSEL_GPCM | \
> +                                       CSPR_V)
> +#define CONFIG_SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
> +#define CONFIG_SYS_FPGA_CSOR           (CSOR_NOR_ADM_SHIFT(4) | \
> +                                       CSOR_NOR_NOR_MODE_AVD_NOR | \
> +                                       CSOR_NOR_TRHZ_80)
> +
> +/* CPLD Timing parameters for IFC GPCM */
> +#define CONFIG_SYS_FPGA_FTIM0          (FTIM0_GPCM_TACSE(0xf) | \
> +                                       FTIM0_GPCM_TEADC(0xf) | \
> +                                       FTIM0_GPCM_TEAHC(0xf))
> +#define CONFIG_SYS_FPGA_FTIM1          (FTIM1_GPCM_TACO(0xff) | \
> +                                       FTIM1_GPCM_TRAD(0x3f))
> +#define CONFIG_SYS_FPGA_FTIM2          (FTIM2_GPCM_TCS(0xf) | \
> +                                       FTIM2_GPCM_TCH(0xf) | \
> +                                       FTIM2_GPCM_TWP(0xff))
> +#define CONFIG_SYS_FPGA_FTIM3           0x0
> +#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_FPGA_CSPR_EXT
> +#define CONFIG_SYS_CSPR0               CONFIG_SYS_FPGA_CSPR
> +#define CONFIG_SYS_AMASK0              CONFIG_SYS_FPGA_AMASK
> +#define CONFIG_SYS_CSOR0               CONFIG_SYS_FPGA_CSOR
> +#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_FPGA_FTIM0
> +#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_FPGA_FTIM1
> +#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_FPGA_FTIM2
> +#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_FPGA_FTIM3
> +
> +/*
> + * Serial Port
> + */
> +#define CONFIG_CONS_INDEX              1
> +#define CONFIG_SYS_NS16550_SERIAL
> +#ifndef CONFIG_DM_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE    1
> +#endif
> +#define CONFIG_SYS_NS16550_CLK         get_serial_clock()
> +
> +#define CONFIG_BAUDRATE                        115200
> +
> +/*
> + * I2C
> + */
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
> +#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
> +#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
> +
> +/* EEPROM */
> +#define CONFIG_ID_EEPROM
> +#define CONFIG_SYS_I2C_EEPROM_NXID
> +#define CONFIG_SYS_EEPROM_BUS_NUM      0
> +#define CONFIG_SYS_I2C_EEPROM_ADDR     0x51
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
> +
> +/* SPI */
> +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
> +/* QSPI */
> +#define FSL_QSPI_FLASH_SIZE            (1 << 24)
> +#define FSL_QSPI_FLASH_NUM             2
> +/* DSPI */
> +#endif
> +
> +#ifdef CONFIG_TSEC_ENET
> +#define CONFIG_ETHPRIME                        "ethernet at 2d10000"

Where does this name come from? Is this not the first mac, i.e. would
you get this without the explicit setting ethprime?

> +#endif
> +
> +/* PCIe */
> +#define CONFIG_PCIE1                   /* PCIE controller 1 */
> +#define CONFIG_PCIE2                   /* PCIE controller 2 */
> +#define FSL_PCIE_COMPAT                        "fsl,ls1021a-pcie"
> +#ifdef CONFIG_PCI
> +#define CONFIG_PCI_SCAN_SHOW
> +#endif
> +
> +#define CONFIG_PEN_ADDR_BIG_ENDIAN
> +#define CONFIG_LAYERSCAPE_NS_ACCESS
> +#define CONFIG_SMP_PEN_ADDR            0x01ee0200
> +#define COUNTER_FREQUENCY              12500000
> +
> +#define CONFIG_HWCONFIG
> +#define HWCONFIG_BUFFER_SIZE           256
> +
> +#define CONFIG_FSL_DEVICE_DISABLE
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +       func(MMC, mmc, 0) \
> +       func(USB, usb, 0) \
> +       func(DHCP, dhcp, na)
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS                                      \
> +       "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0"             \
> +       "initrd_high=0xffffffff\0"                                      \
> +       "fdt_high=0xffffffff\0"                                         \
> +       "fdt_addr=0x64f00000\0"                                         \
> +       "kernel_addr=0x61000000\0"                                      \
> +       "kernelheader_addr=0x60800000\0"                                \
> +       "scriptaddr=0x80000000\0"                                       \
> +       "scripthdraddr=0x80080000\0"                                    \
> +       "fdtheader_addr_r=0x80100000\0"                                 \
> +       "kernelheader_addr_r=0x80200000\0"                              \
> +       "kernel_addr_r=0x80008000\0"                                    \
> +       "kernelheader_size=0x40000\0"                                   \
> +       "fdt_addr_r=0x8f000000\0"                                       \
> +       "ramdisk_addr_r=0xa0000000\0"                                   \
> +       "load_addr=0x80008000\0"                                        \
> +       "kernel_size=0x2800000\0"                                       \
> +       "kernel_addr_sd=0x8000\0"                                       \
> +       "kernel_size_sd=0x14000\0"                                      \
> +       "kernelhdr_addr_sd=0x4000\0"                                    \
> +       "kernelhdr_size_sd=0x10\0"                                      \
> +       BOOTENV                                                         \
> +       "boot_scripts=ls1021atsn_boot.scr\0"                            \
> +       "boot_script_hdr=hdr_ls1021atsn_bs.out\0"                       \
> +               "scan_dev_for_boot_part="                               \
> +                       "part list ${devtype} ${devnum} devplist; "     \
> +                       "env exists devplist || setenv devplist 1; "    \
> +                       "for distro_bootpart in ${devplist}; do "       \
> +                       "if fstype ${devtype} "                         \
> +                               "${devnum}:${distro_bootpart} "         \
> +                               "bootfstype; then "                     \
> +                               "run scan_dev_for_boot; "               \
> +                       "fi; "                                          \
> +               "done\0"                                                \
> +       "scan_dev_for_boot="                                            \
> +               "echo Scanning ${devtype} "                             \
> +                               "${devnum}:${distro_bootpart}...; "     \
> +               "for prefix in ${boot_prefixes}; do "                   \
> +                       "run scan_dev_for_scripts; "                    \
> +                       "run scan_dev_for_extlinux; "                   \
> +               "done;"                                                 \
> +               "\0"                                                    \
> +       "boot_a_script="                                                \
> +               "load ${devtype} ${devnum}:${distro_bootpart} "         \
> +                       "${scriptaddr} ${prefix}${script}; "            \
> +               "env exists secureboot && load ${devtype} "             \
> +                       "${devnum}:${distro_bootpart} "                 \
> +                       "${scripthdraddr} ${prefix}${boot_script_hdr} " \
> +                       "&& esbc_validate ${scripthdraddr};"            \
> +               "source ${scriptaddr}\0"                                \
> +       "qspi_bootcmd=echo Trying load from qspi..;"                    \
> +               "sf probe && sf read $load_addr "                       \
> +               "$kernel_addr $kernel_size; env exists secureboot "     \
> +               "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
> +               "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
> +               "bootm $load_addr#$board\0"                             \
> +       "sd_bootcmd=echo Trying load from SD ..;"                       \
> +               "mmcinfo && mmc read $load_addr "                       \
> +               "$kernel_addr_sd $kernel_size_sd && "                   \
> +               "env exists secureboot && mmc read $kernelheader_addr_r " \
> +               "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
> +               " && esbc_validate ${kernelheader_addr_r};"             \
> +               "bootm $load_addr#$board\0"
> +
> +#undef CONFIG_BOOTCOMMAND
> +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
> +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "    \
> +                          "env exists secureboot && esbc_halt"
> +#elif defined(CONFIG_SD_BOOT)
> +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "      \
> +                          "env exists secureboot && esbc_halt;"
> +#endif
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE              \
> +               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS             16      /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_LOAD_ADDR           0x82000000
> +
> +#define CONFIG_LS102XA_STREAM_ID
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
> +#else
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
> +#endif
> +
> +#define CONFIG_SYS_QE_FW_ADDR          0x67f40000
> +
> +/*
> + * Environment
> + */
> +#define CONFIG_ENV_OVERWRITE
> +
> +#if defined(CONFIG_SD_BOOT)
> +#define CONFIG_ENV_OFFSET              0x300000
> +#define CONFIG_SYS_MMC_ENV_DEV         0
> +#define CONFIG_ENV_SIZE                        0x20000
> +#elif defined(CONFIG_QSPI_BOOT)
> +#define CONFIG_ENV_SIZE                        0x2000
> +#define CONFIG_ENV_OFFSET              0x300000
> +#define CONFIG_ENV_SECT_SIZE           0x40000
> +#endif
> +
> +#define CONFIG_OF_BOARD_SETUP
> +#define CONFIG_OF_STDOUT_VIA_ALIAS
> +#define CONFIG_MISC_INIT_R
> +
> +#include <asm/fsl_secure_boot.h>
> +#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
> +
> +#endif
> --
> 2.17.1
>
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