[U-Boot] [PATCH 6/6] arm: socfpga: gen5: use DM_TIMER for systick

[Simon Goldschmidt]

This removes the ad-hoc timer code in arch.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
---

 arch/arm/dts/socfpga-common-u-boot.dtsi |  8 ++++++++
 arch/arm/mach-socfpga/Kconfig           |  3 +++
 arch/arm/mach-socfpga/Makefile          |  1 -
 arch/arm/mach-socfpga/spl_gen5.c        |  3 ---
 arch/arm/mach-socfpga/timer.c           | 23 -----------------------
 5 files changed, 11 insertions(+), 27 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/timer.c

diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index 270ba99a63..e0305d7fc7 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -5,6 +5,10 @@
  * Copyright (c) 2019 Simon Goldschmidt
  */
 /{
+	chosen {
+		tick-timer = &timer2;
+	};
+
 	soc {
 		u-boot,dm-pre-reloc;
 		clkmgr at ffd04000 {
@@ -16,6 +20,10 @@
 	};
 };
 
+&timer2 {
+	u-boot,dm-pre-reloc;
+};
+
 &rst {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 81052f27d5..518ac8ec4a 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -56,6 +56,9 @@ config TARGET_SOCFPGA_GEN5
 	select CLK
 	select SPL_ALTERA_SDRAM
 	select SPL_CLK if SPL
+	select SPL_TIMER if SPL
+	select TIMER
+	imply DESIGNWARE_APB_TIMER
 	imply FPGA_SOCFPGA
 	imply SPL_SIZE_LIMIT_SUBTRACT_GD
 	imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e66720447f..3b839c9ffd 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -16,7 +16,6 @@ obj-y	+= misc_gen5.o
 obj-y	+= reset_manager_gen5.o
 obj-y	+= scan_manager.o
 obj-y	+= system_manager_gen5.o
-obj-y	+= timer.o
 obj-y	+= wrap_pll_config.o
 obj-y	+= fpga_manager.o
 endif
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 1ae8025746..7a67f538d8 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -103,9 +103,6 @@ void board_init_f(ulong dummy)
 		socfpga_bridges_reset(1);
 	}
 
-	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-	timer_init();
-
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
 	if (cm_basic_init(cm_default_cfg))
diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
deleted file mode 100644
index f1c0262ae5..0000000000
--- a/arch/arm/mach-socfpga/timer.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer.h>
-
-#define TIMER_LOAD_VAL		0xFFFFFFFF
-
-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
-
-/*
- * Timer initialization
- */
-int timer_init(void)
-{
-	writel(TIMER_LOAD_VAL, &timer_base->load_val);
-	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
-	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
-	return 0;
-}
-- 
2.20.1