[U-Boot] [PATCH 3/4] net: mscc: jaguar2: Add ethenet nodes for Jaguar2.
Horatiu Vultur
horatiu.vultur at microchip.com
Tue Mar 5 11:57:40 UTC 2019
Add ethernet nodes for Jaguar2 SoCs family. There are 3 pcb in this
family: pcb110, pcb111 and pcb112.
Signed-off-by: Horatiu Vultur <horatiu.vultur at microchip.com>
---
arch/mips/dts/jr2_pcb110.dts | 67 ++++++++
arch/mips/dts/jr2_pcb111.dts | 352 +++++++++++++++++++++++++++++++++++++++
arch/mips/dts/mscc,jr2.dtsi | 106 ++++++++++++
arch/mips/dts/serval2_pcb112.dts | 39 +++++
4 files changed, 564 insertions(+)
diff --git a/arch/mips/dts/jr2_pcb110.dts b/arch/mips/dts/jr2_pcb110.dts
index ddc30ff..bd89f7c 100644
--- a/arch/mips/dts/jr2_pcb110.dts
+++ b/arch/mips/dts/jr2_pcb110.dts
@@ -72,3 +72,70 @@
sgpio-ports = <0x3f00ffff>;
gpio-ranges = <&sgpio2 0 0 96>;
};
+
+&mdio1 {
+ status = "okay";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy at 2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy at 3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy at 4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy at 5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy at 6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy at 7 {
+ reg = <7>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+
+ port0: port at 0 {
+ reg = <0>;
+ phy-handle = <&phy0>;
+ };
+ port1: port at 1 {
+ reg = <1>;
+ phy-handle = <&phy1>;
+ };
+ port2: port at 2 {
+ reg = <2>;
+ phy-handle = <&phy2>;
+ };
+ port3: port at 3 {
+ reg = <3>;
+ phy-handle = <&phy3>;
+ };
+ port4: port at 4 {
+ reg = <4>;
+ phy-handle = <&phy4>;
+ };
+ port5: port at 5 {
+ reg = <5>;
+ phy-handle = <&phy5>;
+ };
+ port6: port at 6 {
+ reg = <6>;
+ phy-handle = <&phy6>;
+ };
+ port7: port at 7 {
+ reg = <7>;
+ phy-handle = <&phy7>;
+ };
+ };
+};
diff --git a/arch/mips/dts/jr2_pcb111.dts b/arch/mips/dts/jr2_pcb111.dts
index 4d411b6..8b616c8 100644
--- a/arch/mips/dts/jr2_pcb111.dts
+++ b/arch/mips/dts/jr2_pcb111.dts
@@ -72,3 +72,355 @@
sgpio-ports = <0xff000000>;
gpio-ranges = <&sgpio2 0 0 96>;
};
+
+&mdio1 {
+ status = "okay";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy at 2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy at 3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy at 4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy at 5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy at 6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy at 7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy at 8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy at 9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy at 10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy at 11 {
+ reg = <11>;
+ };
+ phy12: ethernet-phy at 12 {
+ reg = <12>;
+ };
+ phy13: ethernet-phy at 13 {
+ reg = <13>;
+ };
+ phy14: ethernet-phy at 14 {
+ reg = <14>;
+ };
+ phy15: ethernet-phy at 15 {
+ reg = <15>;
+ };
+ phy16: ethernet-phy at 16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy at 17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy at 18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy at 19 {
+ reg = <19>;
+ };
+ phy20: ethernet-phy at 20 {
+ reg = <20>;
+ };
+ phy21: ethernet-phy at 21 {
+ reg = <21>;
+ };
+ phy22: ethernet-phy at 22 {
+ reg = <22>;
+ };
+ phy23: ethernet-phy at 23 {
+ reg = <23>;
+ };
+};
+
+&mdio2 {
+ status = "okay";
+
+ phy24: ethernet-phy at 24 {
+ reg = <0>;
+ };
+ phy25: ethernet-phy at 25 {
+ reg = <1>;
+ };
+ phy26: ethernet-phy at 26 {
+ reg = <2>;
+ };
+ phy27: ethernet-phy at 27 {
+ reg = <3>;
+ };
+ phy28: ethernet-phy at 28 {
+ reg = <4>;
+ };
+ phy29: ethernet-phy at 29 {
+ reg = <5>;
+ };
+ phy30: ethernet-phy at 30 {
+ reg = <6>;
+ };
+ phy31: ethernet-phy at 31 {
+ reg = <7>;
+ };
+ phy32: ethernet-phy at 32 {
+ reg = <8>;
+ };
+ phy33: ethernet-phy at 33 {
+ reg = <9>;
+ };
+ phy34: ethernet-phy at 34 {
+ reg = <10>;
+ };
+ phy35: ethernet-phy at 35 {
+ reg = <11>;
+ };
+ phy36: ethernet-phy at 36 {
+ reg = <12>;
+ };
+ phy37: ethernet-phy at 37 {
+ reg = <13>;
+ };
+ phy38: ethernet-phy at 38 {
+ reg = <14>;
+ };
+ phy39: ethernet-phy at 39 {
+ reg = <15>;
+ };
+ phy40: ethernet-phy at 40 {
+ reg = <16>;
+ };
+ phy41: ethernet-phy at 41 {
+ reg = <17>;
+ };
+ phy42: ethernet-phy at 42 {
+ reg = <18>;
+ };
+ phy43: ethernet-phy at 43 {
+ reg = <19>;
+ };
+ phy44: ethernet-phy at 44 {
+ reg = <20>;
+ };
+ phy45: ethernet-phy at 45 {
+ reg = <21>;
+ };
+ phy46: ethernet-phy at 46 {
+ reg = <22>;
+ };
+ phy47: ethernet-phy at 47 {
+ reg = <23>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+ port0: port at 0 {
+ reg = <0>;
+ phy-handle = <&phy0>;
+ };
+ port1: port at 1 {
+ reg = <1>;
+ phy-handle = <&phy1>;
+ };
+ port2: port at 2 {
+ reg = <2>;
+ phy-handle = <&phy2>;
+ };
+ port3: port at 3 {
+ reg = <3>;
+ phy-handle = <&phy3>;
+ };
+ port4: port at 4 {
+ reg = <4>;
+ phy-handle = <&phy4>;
+ };
+ port5: port at 5 {
+ reg = <5>;
+ phy-handle = <&phy5>;
+ };
+ port6: port at 6 {
+ reg = <6>;
+ phy-handle = <&phy6>;
+ };
+ port7: port at 7 {
+ reg = <7>;
+ phy-handle = <&phy7>;
+ };
+ port8: port at 8 {
+ reg = <8>;
+ phy-handle = <&phy8>;
+ };
+ port9: port at 9 {
+ reg = <9>;
+ phy-handle = <&phy9>;
+ };
+ port10: port at 10 {
+ reg = <10>;
+ phy-handle = <&phy10>;
+ };
+ port11: port at 11 {
+ reg = <11>;
+ phy-handle = <&phy11>;
+ };
+ port12: port at 12 {
+ reg = <12>;
+ phy-handle = <&phy12>;
+ };
+ port13: port at 13 {
+ reg = <13>;
+ phy-handle = <&phy13>;
+ };
+ port14: port at 14 {
+ reg = <14>;
+ phy-handle = <&phy14>;
+ };
+ port15: port at 15 {
+ reg = <15>;
+ phy-handle = <&phy15>;
+ };
+ port16: port at 16 {
+ reg = <16>;
+ phy-handle = <&phy16>;
+ };
+ port17: port at 17 {
+ reg = <17>;
+ phy-handle = <&phy17>;
+ };
+ port18: port at 18 {
+ reg = <18>;
+ phy-handle = <&phy18>;
+ };
+ port19: port at 19 {
+ reg = <19>;
+ phy-handle = <&phy19>;
+ };
+ port20: port at 20 {
+ reg = <20>;
+ phy-handle = <&phy20>;
+ };
+ port21: port at 21 {
+ reg = <21>;
+ phy-handle = <&phy21>;
+ };
+ port22: port at 22 {
+ reg = <22>;
+ phy-handle = <&phy22>;
+ };
+ port23: port at 23 {
+ reg = <23>;
+ phy-handle = <&phy23>;
+ };
+ port24: port at 24 {
+ reg = <24>;
+ phy-handle = <&phy24>;
+ };
+ port25: port at 25 {
+ reg = <25>;
+ phy-handle = <&phy25>;
+ };
+ port26: port at 26 {
+ reg = <26>;
+ phy-handle = <&phy26>;
+ };
+ port27: port at 27 {
+ reg = <27>;
+ phy-handle = <&phy27>;
+ };
+ port28: port at 28 {
+ reg = <28>;
+ phy-handle = <&phy28>;
+ };
+ port29: port at 29 {
+ reg = <29>;
+ phy-handle = <&phy29>;
+ };
+ port30: port at 30 {
+ reg = <30>;
+ phy-handle = <&phy30>;
+ };
+ port31: port at 31 {
+ reg = <31>;
+ phy-handle = <&phy31>;
+ };
+ port32: port at 32 {
+ reg = <32>;
+ phy-handle = <&phy32>;
+ };
+ port33: port at 33 {
+ reg = <33>;
+ phy-handle = <&phy33>;
+ };
+ port34: port at 34 {
+ reg = <34>;
+ phy-handle = <&phy34>;
+ };
+ port35: port at 35 {
+ reg = <35>;
+ phy-handle = <&phy35>;
+ };
+ port36: port at 36 {
+ reg = <36>;
+ phy-handle = <&phy36>;
+ };
+ port37: port at 37 {
+ reg = <37>;
+ phy-handle = <&phy37>;
+ };
+ port38: port at 38 {
+ reg = <38>;
+ phy-handle = <&phy38>;
+ };
+ port39: port at 39 {
+ reg = <39>;
+ phy-handle = <&phy39>;
+ };
+ port40: port at 40 {
+ reg = <40>;
+ phy-handle = <&phy40>;
+ };
+ port41: port at 41 {
+ reg = <41>;
+ phy-handle = <&phy41>;
+ };
+ port42: port at 42 {
+ reg = <42>;
+ phy-handle = <&phy42>;
+ };
+ port43: port at 43 {
+ reg = <43>;
+ phy-handle = <&phy43>;
+ };
+ port44: port at 44 {
+ reg = <44>;
+ phy-handle = <&phy44>;
+ };
+ port45: port at 45 {
+ reg = <45>;
+ phy-handle = <&phy45>;
+ };
+ port46: port at 46 {
+ reg = <46>;
+ phy-handle = <&phy46>;
+ };
+ port47: port at 47 {
+ reg = <47>;
+ phy-handle = <&phy47>;
+ };
+
+ };
+};
diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
index 0900926..9592b52 100644
--- a/arch/mips/dts/mscc,jr2.dtsi
+++ b/arch/mips/dts/mscc,jr2.dtsi
@@ -183,5 +183,111 @@
gpio-bank-name = "sgpio2_";
sgpio-clock = <0x14>;
};
+
+ switch: switch at 1010000 {
+ compatible = "mscc,vsc7454-switch";
+ reg = <0x01040000 0x0100>, // VTSS_TO_DEV_0
+ <0x01050000 0x0100>, // VTSS_TO_DEV_1
+ <0x01060000 0x0100>, // VTSS_TO_DEV_2
+ <0x01070000 0x0100>, // VTSS_TO_DEV_3
+ <0x01080000 0x0100>, // VTSS_TO_DEV_4
+ <0x01090000 0x0100>, // VTSS_TO_DEV_5
+ <0x010a0000 0x0100>, // VTSS_TO_DEV_6
+ <0x010b0000 0x0100>, // VTSS_TO_DEV_7
+ <0x010c0000 0x0100>, // VTSS_TO_DEV_8
+ <0x010d0000 0x0100>, // VTSS_TO_DEV_9
+ <0x010e0000 0x0100>, // VTSS_TO_DEV_10
+ <0x010f0000 0x0100>, // VTSS_TO_DEV_11
+ <0x01100000 0x0100>, // VTSS_TO_DEV_12
+ <0x01110000 0x0100>, // VTSS_TO_DEV_13
+ <0x01120000 0x0100>, // VTSS_TO_DEV_14
+ <0x01130000 0x0100>, // VTSS_TO_DEV_15
+ <0x01140000 0x0100>, // VTSS_TO_DEV_16
+ <0x01150000 0x0100>, // VTSS_TO_DEV_17
+ <0x01160000 0x0100>, // VTSS_TO_DEV_18
+ <0x01170000 0x0100>, // VTSS_TO_DEV_19
+ <0x01180000 0x0100>, // VTSS_TO_DEV_20
+ <0x01190000 0x0100>, // VTSS_TO_DEV_21
+ <0x011a0000 0x0100>, // VTSS_TO_DEV_22
+ <0x011b0000 0x0100>, // VTSS_TO_DEV_23
+ <0x011c0000 0x0100>, // VTSS_TO_DEV_24
+ <0x011d0000 0x0100>, // VTSS_TO_DEV_25
+ <0x011e0000 0x0100>, // VTSS_TO_DEV_26
+ <0x011f0000 0x0100>, // VTSS_TO_DEV_27
+ <0x01200000 0x0100>, // VTSS_TO_DEV_28
+ <0x01210000 0x0100>, // VTSS_TO_DEV_29
+ <0x01220000 0x0100>, // VTSS_TO_DEV_30
+ <0x01230000 0x0100>, // VTSS_TO_DEV_31
+ <0x01240000 0x0100>, // VTSS_TO_DEV_32
+ <0x01250000 0x0100>, // VTSS_TO_DEV_33
+ <0x01260000 0x0100>, // VTSS_TO_DEV_34
+ <0x01270000 0x0100>, // VTSS_TO_DEV_35
+ <0x01280000 0x0100>, // VTSS_TO_DEV_36
+ <0x01290000 0x0100>, // VTSS_TO_DEV_37
+ <0x012a0000 0x0100>, // VTSS_TO_DEV_38
+ <0x012b0000 0x0100>, // VTSS_TO_DEV_39
+ <0x012c0000 0x0100>, // VTSS_TO_DEV_40
+ <0x012d0000 0x0100>, // VTSS_TO_DEV_41
+ <0x012e0000 0x0100>, // VTSS_TO_DEV_42
+ <0x012f0000 0x0100>, // VTSS_TO_DEV_43
+ <0x01300000 0x0100>, // VTSS_TO_DEV_44
+ <0x01310000 0x0100>, // VTSS_TO_DEV_45
+ <0x01320000 0x0100>, // VTSS_TO_DEV_46
+ <0x01330000 0x0100>, // VTSS_TO_DEV_47
+ <0x01f00000 0x100000>, // ANA_AC
+ <0x01d00000 0x100000>, // ANA_CL
+ <0x01e00000 0x100000>, // ANA_L2
+ <0x01410000 0x10000>, // ASM
+ <0x01460000 0x10000>, // HSIO
+ <0x01420000 0x00000>, // LRN
+ <0x017d0000 0x10000>, // QFWD
+ <0x01020000 0x20000>, // QS
+ <0x017e0000 0x10000>, // QSYS
+ <0x01b00000 0x80000>; // REW
+ reg-names = "port0", "port1", "port2", "port3", "port4",
+ "port5", "port6", "port7", "port8", "port9",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port18", "port19", "port20", "port21",
+ "port22", "port23", "port24", "port25",
+ "port26", "port27", "port28", "port29",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port38", "port39", "port40", "port41",
+ "port42", "port43", "port44", "port45",
+ "port46", "port47", "ana_ac", "ana_cl",
+ "ana_l2", "asm", "hsio", "lrn", "qfwd",
+ "qs", "qsys", "rew";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio0: mdio at 010100c8 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,jr2-miim";
+ reg = <0x010100c8 0x24>;
+ status = "disabled";
+ };
+
+ mdio1: mdio at 010100ec {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,jr2-miim";
+ reg = <0x010100ec 0x24>;
+ status = "disabled";
+ };
+
+ mdio2: mdio at 01010110 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,jr2-miim";
+ reg = <0x01010110 0x24>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/mips/dts/serval2_pcb112.dts b/arch/mips/dts/serval2_pcb112.dts
index fe025f4..3353a0b 100644
--- a/arch/mips/dts/serval2_pcb112.dts
+++ b/arch/mips/dts/serval2_pcb112.dts
@@ -58,3 +58,42 @@
status = "okay";
sgpio-ports = <0x3fe0ffff>;
};
+
+&mdio0 {
+ status = "okay";
+
+ phy16: ethernet-phy at 16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy at 17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy at 18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy at 19 {
+ reg = <19>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+
+ port0: port at 0 {
+ reg = <24>;
+ phy-handle = <&phy16>;
+ };
+ port1: port at 1 {
+ reg = <25>;
+ phy-handle = <&phy17>;
+ };
+ port2: port at 2 {
+ reg = <26>;
+ phy-handle = <&phy18>;
+ };
+ port3: port at 3 {
+ reg = <27>;
+ phy-handle = <&phy19>;
+ };
+ };
+};
--
2.7.4
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