[U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
Horatiu Vultur
horatiu.vultur at microchip.com
Sun Mar 24 15:59:47 UTC 2019
Hi Daniel,
The 03/15/2019 13:02, Daniel Schwierzeck wrote:
> External E-Mail
>
>
> Hi Horatio,
>
> Am 06.03.19 um 23:11 schrieb Horatiu Vultur:
> > Hi Daniel,
> >
> > The 03/06/2019 14:19, Daniel Schwierzeck wrote:
> >>
> >>
> >> Am 05.03.19 um 12:57 schrieb Horatiu Vultur:
> >>> In Jaguar2 SoC family there are 3 different pcb. Each of this needs
> >>> to configure the SerDes and the phys in different ways.
> >>> Therefore implement the function board_phy_config and serdes_cfg
> >>> and based on pcb configure them accordingly.
> >>
> >> what are the differences between all boards? Can't you model the
> >> different register values somehow as custom DT properties? This method
> >> looks like a lot of code duplication and doesn't scale well when adding
> >> new boards.
> >
> > So there are following boards:
> > - pcb110: it has viper phys that are connected to serdes1g using the
> > interface sgmii
> > - pcb111: it has atom phys that are connected to serdes6g using the
> > interface qsgmii
> > - pcb112: it has viper phys that are connected to serdes6g using the
> > interface sgmii.
> >
> > Do you have an example where I can look, how to add this custom
> > properties?
> >
> > Yes, it looks like a lot code duplication, but there are only few
> > differences between them. I was thinking maybe I can create 2 functions
> > that configure the serdes1g and serdes6g which will get as a paramenter
> > the interface mode. In this way I think it would scale better, because
> > then each new board it would just call these new functions.
> >
> > /Horatiu
>
> but this code belongs to the ethernet driver. Board specific differences
> like PHY interface or Serdes type could be configured via appropiate
> device-tree bindings (PHY interface already exists as generic binding).
> How do you plan to do it in Linux?
I understand now. Currently there is no Jaguar2 support on the upstream
kernel, maybe at a later point in time will come this.
>
> I've found Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt
> which looks very similar to what you want to achieve here. Maybe the
> Bootlin guys can give you some more hints ;)
I managed to talk with Alexandre and he proposed to have a look over the
comphy inside the u-boot. Therefore I will have a look over this and I
will send a new patch series. Thank you.
>
>
> >
> >>
> >>>
> >>> Signed-off-by: Horatiu Vultur <horatiu.vultur at microchip.com>
> >>> ---
> >>> board/mscc/jr2/jr2.c | 542 +++++++++++++++++++++++++++++++++++++++++++++++++++
> >>> 1 file changed, 542 insertions(+)
> >>>
> >>> diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
> >>> index 58a4a04..94e0c5d 100644
> >>> --- a/board/mscc/jr2/jr2.c
> >>> +++ b/board/mscc/jr2/jr2.c
> >>> @@ -6,6 +6,140 @@
> >>> #include <common.h>
> >>> #include <asm/io.h>
> >>> #include <led.h>
> >>> +#include <miiphy.h>
> >>> +
> >>> +#define HSIO_ANA_SERDES1G_DES_CFG 0xac
> >>> +#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
> >>> +#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
> >>> +#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
> >>> +#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19)
> >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
> >>> +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4
> >>> +#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
> >>> +#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
> >>> +#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
> >>> +#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
> >>> +#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
> >>> +#define HSIO_ANA_SERDES1G_SER_CFG 0xb8
> >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc
> >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
> >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
> >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
> >>> +#define HSIO_ANA_SERDES1G_PLL_CFG 0xc0
> >>> +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
> >>> +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
> >>> +#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
> >>> +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8
> >>> +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4
> >>> +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc
> >>> +#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
> >>> +#define HSIO_MCB_SERDES1G_CFG 0xe8
> >>> +#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
> >>> +#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
> >>> +
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG 0x11c
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG_SWAP_ANA BIT(0)
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG_BW_ANA(x) ((x) << 1)
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG_SWAP_HYST BIT(4)
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG_BW_HYST(x) ((x) << 5)
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG_CPMD_SEL(x) ((x) << 8)
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG_MBTR_CTRL(x) ((x) << 10)
> >>> +#define HSIO_ANA_SERDES6G_DES_CFG_PHS_CTRL(x) ((x) << 13)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG 0x120
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_REG_ENA BIT(0)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA BIT(1)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA BIT(2)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA BIT(3)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_CONCUR BIT(4)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA BIT(5)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(x) ((x) << 7)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(x) ((x) << 9)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(x) ((x) << 11)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(x) ((x) << 13)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(x) ((x) << 15)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(x) ((x) << 18)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(x) ((x) << 20)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(x) ((x) << 24)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL BIT(28)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG_SOFSI(x) ((x) << 29)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1 0x124
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1_FILT_OFFSET BIT(4)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1_FILT_LP BIT(5)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1_FILT_MID BIT(6)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1_FILT_HP BIT(7)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1_SCALY(x) ((x) << 8)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1_TSDET(x) ((x) << 12)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(x) ((x) << 17)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2 0x128
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2_UREG(x) (x)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2_UMAX(x) ((x) << 3)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2_TCALV(x) ((x) << 5)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2_OCALS(x) ((x) << 10)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2_OINFS(x) ((x) << 16)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2_OINFI(x) ((x) << 22)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG2_TINFV(x) ((x) << 27)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG3 0x12c
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG3_INI_OFFSET(x) (x)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG3_INI_LP(x) ((x) << 6)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG3_INI_MID(x) ((x) << 12)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG3_INI_HP(x) ((x) << 18)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4 0x130
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MAX_OFFSET(x) (x)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MAX_LP(x) ((x) << 6)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MAX_MID(x) ((x) << 12)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MAX_HP(x) ((x) << 18)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG5 0x134
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MIN_OFFSET(x) (x)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MIN_LP(x) ((x) << 6)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MIN_MID(x) ((x) << 12)
> >>> +#define HSIO_ANA_SERDES6G_IB_CFG4_MIN_HP(x) ((x) << 18)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG 0x138
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_RESISTOR_CTRL(x) (x)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_SR(x) ((x) << 4)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_SR_H BIT(8)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_SEL_RCTRL BIT(9)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_R_COR BIT(10)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_POST1(x) ((x) << 11)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_R_ADJ_PDR BIT(16)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_R_ADJ_MUX BIT(17)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_PREC(x) ((x) << 18)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_POST0(x) ((x) << 23)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_POL BIT(29)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_ENA1V_MODE BIT(30)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG_IDLE BIT(31)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG1 0x13c
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG1_LEV(x) (x)
> >>> +#define HSIO_ANA_SERDES6G_OB_CFG1_ENA_CAS(x) ((x) << 6)
> >>> +#define HSIO_ANA_SERDES6G_SER_CFG 0x140
> >>> +#define HSIO_ANA_SERDES6G_COMMON_CFG 0x144
> >>> +#define HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(x) (x)
> >>> +#define HSIO_ANA_SERDES6G_COMMON_CFG_QRATE BIT(2)
> >>> +#define HSIO_ANA_SERDES6G_COMMON_CFG_ENA_LANE BIT(14)
> >>> +#define HSIO_ANA_SERDES6G_COMMON_CFG_SYS_RST BIT(16)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG 0x148
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_ROT_FRQ BIT(0)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_ROT_DIR BIT(1)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_RB_DATA_SEL BIT(2)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_FSM_OOR_RECAL_ENA BIT(3)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_FSM_FORCE_SET_ENA BIT(4)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_FSM_ENA BIT(5)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 6)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_ENA_ROT BIT(14)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_DIV4 BIT(15)
> >>> +#define HSIO_ANA_SERDES6G_PLL_CFG_ENA_OFFS(x) ((x) << 16)
> >>> +#define HSIO_DIG_SERDES6G_MISC_CFG 0x108
> >>> +#define HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST BIT(0)
> >>> +#define HSIO_MCB_SERDES6G_CFG 0x168
> >>> +#define HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT BIT(31)
> >>> +#define HSIO_MCB_SERDES6G_CFG_ADDR(x) (x)
> >>> +#define HSIO_HW_CFGSTAT_HW_CFG 0x16c
> >>>
> >>> enum {
> >>> BOARD_TYPE_PCB110 = 0xAABBCE00,
> >>> @@ -64,6 +198,414 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode)
> >>> }
> >>> }
> >>>
> >>> +int board_phy_config(struct phy_device *phydev)
> >>> +{
> >>> + if (gd->board_type == BOARD_TYPE_PCB110 ||
> >>> + gd->board_type == BOARD_TYPE_PCB112) {
> >>> + phy_write(phydev, 0, 31, 0x10);
> >>> + phy_write(phydev, 0, 18, 0x80F0);
> >>> + while (phy_read(phydev, 0, 18) & 0x8000)
> >>> + ;
> >>> + phy_write(phydev, 0, 31, 0);
> >>> + }
> >>> + if (gd->board_type == BOARD_TYPE_PCB111) {
> >>> + phy_write(phydev, 0, 31, 0x10);
> >>> + phy_write(phydev, 0, 18, 0x80A0);
> >>> + while (phy_read(phydev, 0, 18) & 0x8000)
> >>> + ;
> >>> + phy_write(phydev, 0, 14, 0x800);
> >>> + phy_write(phydev, 0, 31, 0);
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static void serdes6g_write(void __iomem *base, u32 addr)
> >>> +{
> >>> + u32 data;
> >>> +
> >>> + writel(HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT |
> >>> + HSIO_MCB_SERDES6G_CFG_ADDR(addr),
> >>> + base + HSIO_MCB_SERDES6G_CFG);
> >>> +
> >>> + do {
> >>> + data = readl(base + HSIO_MCB_SERDES6G_CFG);
> >>> + } while (data & HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT);
> >>> +
> >>> + mdelay(100);
> >>> +}
> >>> +
> >>> +static void serdes6g_pcb111_cfg(void __iomem *base)
> >>> +{
> >>> + /* sets serdes6g in QSGMII mode */
> >>> + writel(0xfff, base + HSIO_HW_CFGSTAT_HW_CFG);
> >>> +
> >>> + writel(HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(3),
> >>> + base + HSIO_ANA_SERDES6G_COMMON_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(120) |
> >>> + HSIO_ANA_SERDES6G_PLL_CFG_ENA_OFFS(3),
> >>> + base + HSIO_ANA_SERDES6G_PLL_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(7) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG1_FILT_OFFSET |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_LP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_MID |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_HP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_SCALY(15) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TSDET(3) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG1);
> >>> + writel(HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST,
> >>> + base + HSIO_DIG_SERDES6G_MISC_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xfff0);
> >>> +
> >>> + writel(HSIO_ANA_SERDES6G_OB_CFG_RESISTOR_CTRL(1) |
> >>> + HSIO_ANA_SERDES6G_OB_CFG_SR(7) |
> >>> + HSIO_ANA_SERDES6G_OB_CFG_SR_H |
> >>> + HSIO_ANA_SERDES6G_OB_CFG_POL, base + HSIO_ANA_SERDES6G_OB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_OB_CFG1_LEV(24),
> >>> + base + HSIO_ANA_SERDES6G_OB_CFG1);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG1_FILT_OFFSET |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_LP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_MID |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_HP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_SCALY(15) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TSDET(16) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG1);
> >>> + writel(0x0, base + HSIO_ANA_SERDES6G_SER_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(3) |
> >>> + HSIO_ANA_SERDES6G_COMMON_CFG_ENA_LANE |
> >>> + HSIO_ANA_SERDES6G_COMMON_CFG_SYS_RST,
> >>> + base + HSIO_ANA_SERDES6G_COMMON_CFG);
> >>> + writel(HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST,
> >>> + base + HSIO_DIG_SERDES6G_MISC_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xfff0);
> >>> +
> >>> + /* set pll_fsm_ena = 1 */
> >>> + writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_ENA |
> >>> + HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(120) |
> >>> + HSIO_ANA_SERDES6G_PLL_CFG_ENA_OFFS(3),
> >>> + base + HSIO_ANA_SERDES6G_PLL_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xfff0);
> >>> +
> >>> + /* wait 20ms for pll bringup */
> >>> + mdelay(20);
> >>> +
> >>> + /* start IB calibration by setting ib_cal_ena and clearing lane_rst */
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(0x0, base + HSIO_DIG_SERDES6G_MISC_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xfff0);
> >>> +
> >>> + /* wait 60 for calibration */
> >>> + mdelay(60);
> >>> +
> >>> + /* set ib_tsdet and ib_reg_pat_sel_offset back to correct values */
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CAL_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(7) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG1_FILT_OFFSET |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_LP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_MID |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_HP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_SCALY(15) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TSDET(16) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG1);
> >>> +
> >>> + serdes6g_write(base, 0xfff0);
> >>> +}
> >>> +
> >>> +static void serdes6g_pcb112_cfg(void __iomem *base)
> >>> +{
> >>> + /* sets serdes6g in SGMII mode */
> >>> + writel(HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(3),
> >>> + base + HSIO_ANA_SERDES6G_COMMON_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(120) |
> >>> + HSIO_ANA_SERDES6G_PLL_CFG_ENA_OFFS(3),
> >>> + base + HSIO_ANA_SERDES6G_PLL_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(7) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG1_FILT_OFFSET |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_LP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_MID |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_HP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_SCALY(15) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TSDET(3) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG1);
> >>> + writel(HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST,
> >>> + base + HSIO_DIG_SERDES6G_MISC_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xf);
> >>> +
> >>> + writel(HSIO_ANA_SERDES6G_OB_CFG_RESISTOR_CTRL(1) |
> >>> + HSIO_ANA_SERDES6G_OB_CFG_SR(7) |
> >>> + HSIO_ANA_SERDES6G_OB_CFG_SR_H |
> >>> + HSIO_ANA_SERDES6G_OB_CFG_POL |
> >>> + HSIO_ANA_SERDES6G_OB_CFG_ENA1V_MODE,
> >>> + base + HSIO_ANA_SERDES6G_OB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_OB_CFG1_LEV(48) |
> >>> + HSIO_ANA_SERDES6G_OB_CFG1_ENA_CAS(2),
> >>> + base + HSIO_ANA_SERDES6G_OB_CFG1);
> >>> + writel(HSIO_ANA_SERDES6G_DES_CFG_BW_ANA(3) |
> >>> + HSIO_ANA_SERDES6G_DES_CFG_BW_HYST(5) |
> >>> + HSIO_ANA_SERDES6G_DES_CFG_MBTR_CTRL(2) |
> >>> + HSIO_ANA_SERDES6G_DES_CFG_PHS_CTRL(6),
> >>> + base + HSIO_ANA_SERDES6G_DES_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG1_FILT_OFFSET |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_LP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_MID |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_HP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_SCALY(15) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TSDET(16) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG1);
> >>> + writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(60) |
> >>> + HSIO_ANA_SERDES6G_PLL_CFG_ENA_OFFS(3),
> >>> + base + HSIO_ANA_SERDES6G_PLL_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_COMMON_CFG_IF_MODE(1) |
> >>> + HSIO_ANA_SERDES6G_COMMON_CFG_QRATE |
> >>> + HSIO_ANA_SERDES6G_COMMON_CFG_ENA_LANE |
> >>> + HSIO_ANA_SERDES6G_COMMON_CFG_SYS_RST,
> >>> + base + HSIO_ANA_SERDES6G_COMMON_CFG);
> >>> + writel(0x0, base + HSIO_ANA_SERDES6G_SER_CFG);
> >>> + writel(HSIO_DIG_SERDES6G_MISC_CFG_LANE_RST,
> >>> + base + HSIO_DIG_SERDES6G_MISC_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xf);
> >>> +
> >>> + /* set pll_fsm_ena = 1 */
> >>> + writel(HSIO_ANA_SERDES6G_PLL_CFG_FSM_ENA |
> >>> + HSIO_ANA_SERDES6G_PLL_CFG_FSM_CTRL_DATA(60) |
> >>> + HSIO_ANA_SERDES6G_PLL_CFG_ENA_OFFS(3),
> >>> + base + HSIO_ANA_SERDES6G_PLL_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xf);
> >>> +
> >>> + /* wait 20ms for pll bringup */
> >>> + mdelay(20);
> >>> +
> >>> + /* start IB calibration by setting ib_cal_ena and clearing lane_rst */
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(0x0, base + HSIO_DIG_SERDES6G_MISC_CFG);
> >>> +
> >>> + serdes6g_write(base, 0xf);
> >>> +
> >>> + /* wait 60ms for calibration */
> >>> + mdelay(60);
> >>> +
> >>> + /* set ib_tsdet and ib_reg_pat_sel_offset back to correct values */
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG_REG_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SAM_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_CONCUR |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENA |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(0) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(2) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(7) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(1) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(5) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(13) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_VBULK_SEL |
> >>> + HSIO_ANA_SERDES6G_IB_CFG_SOFSI(1),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG);
> >>> + writel(HSIO_ANA_SERDES6G_IB_CFG1_FILT_OFFSET |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_LP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_MID |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_FILT_HP |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_SCALY(15) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TSDET(3) |
> >>> + HSIO_ANA_SERDES6G_IB_CFG1_TJTAG(8),
> >>> + base + HSIO_ANA_SERDES6G_IB_CFG1);
> >>> +
> >>> + serdes6g_write(base, 0xf);
> >>> +}
> >>> +
> >>> +static void serdes_write(void __iomem *base, u32 addr)
> >>> +{
> >>> + u32 data;
> >>> +
> >>> + writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
> >>> + HSIO_MCB_SERDES1G_CFG_ADDR(addr),
> >>> + base + HSIO_MCB_SERDES1G_CFG);
> >>> +
> >>> + do {
> >>> + data = readl(base + HSIO_MCB_SERDES1G_CFG);
> >>> + } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
> >>> +
> >>> + mdelay(100);
> >>> +}
> >>> +
> >>> +static void serdes1g_pcb110_cfg(void __iomem *base)
> >>> +{
> >>> + writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
> >>> + writel(0x0, base + HSIO_DIG_SERDES1G_TP_CFG);
> >>> + writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
> >>> + writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
> >>> + HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
> >>> + HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
> >>> + HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
> >>> + HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
> >>> + base + HSIO_ANA_SERDES1G_OB_CFG);
> >>> + writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(13) |
> >>> + HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(2) |
> >>> + HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
> >>> + HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV |
> >>> + HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
> >>> + HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(3) |
> >>> + HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
> >>> + base + HSIO_ANA_SERDES1G_IB_CFG);
> >>> + writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
> >>> + HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
> >>> + HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
> >>> + HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
> >>> + base + HSIO_ANA_SERDES1G_DES_CFG);
> >>> + writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
> >>> + base + HSIO_DIG_SERDES1G_MISC_CFG);
> >>> + writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
> >>> + HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(0xc8) |
> >>> + HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
> >>> + base + HSIO_ANA_SERDES1G_PLL_CFG);
> >>> + writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
> >>> + HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
> >>> + HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
> >>> + base + HSIO_ANA_SERDES1G_COMMON_CFG);
> >>> +
> >>> + serdes_write(base, 0x1fe);
> >>> +
> >>> + setbits_le32(base + HSIO_ANA_SERDES1G_COMMON_CFG,
> >>> + HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST);
> >>> +
> >>> + serdes_write(base, 0x1fe);
> >>> +
> >>> + clrbits_le32(base + HSIO_DIG_SERDES1G_MISC_CFG,
> >>> + HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST);
> >>> +
> >>> + serdes_write(base, 0x1fe);
> >>> +}
> >>> +
> >>> +void serdes_cfg(void __iomem *base)
> >>> +{
> >>> + if (gd->board_type == BOARD_TYPE_PCB111)
> >>> + return serdes6g_pcb111_cfg(base);
> >>> + if (gd->board_type == BOARD_TYPE_PCB112)
> >>> + return serdes6g_pcb112_cfg(base);
> >>> + if (gd->board_type == BOARD_TYPE_PCB110)
> >>> + return serdes1g_pcb110_cfg(base);
> >>> +}
> >>> +
> >>> void board_debug_uart_init(void)
> >>> {
> >>> /* too early for the pinctrl driver, so configure the UART pins here */
> >>>
> >>
> >> --
> >> - Daniel
> >
>
> --
> - Daniel
--
/Horatiu
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