[U-Boot] [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0

[Bin Meng]

On Mon, Mar 18, 2019 at 2:29 AM Lukas Auer
<lukas.auer at aisec.fraunhofer.de> wrote:
>
> The hart ID passed by the previous boot stage is currently stored in
> register s0. If we divert the control flow inside a function, which is
> required as part of multi-hart support, the function epilog may not be
> called, clobbering register s0. Save the hart ID in the unallocatable
> register tp instead to protect the hart ID.
>
> Signed-off-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> ---
>
> Changes in v3:
> - New patch to save the hart ID in register tp instead of s0
>
> Changes in v2: None
>
>  arch/riscv/cpu/start.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>