[U-Boot] [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0

[Rick Chen]

> > From: Lukas Auer [mailto:lukas.auer at aisec.fraunhofer.de]
> > Sent: Monday, March 18, 2019 2:29 AM
> > To: u-boot at lists.denx.de
> > Cc: Anup Patel; Andreas Schwab; Bin Meng; Atish Patra; Palmer Dabbelt; Lukas
> > Auer; Atish Patra; Anup Patel; Rick Jian-Zhi Chen(陳建志)
> > Subject: [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0
> >
> > The hart ID passed by the previous boot stage is currently stored in register s0. If
> > we divert the control flow inside a function, which is required as part of
> > multi-hart support, the function epilog may not be called, clobbering register s0.
> > Save the hart ID in the unallocatable register tp instead to protect the hart ID.
> >
> > Signed-off-by: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> > ---
> >
> > Changes in v3:
> > - New patch to save the hart ID in register tp instead of s0
> >
> > Changes in v2: None
> >
> >  arch/riscv/cpu/start.S | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index
> > a30f6f7194..bcc0ff696d 100644
> > --- a/arch/riscv/cpu/start.S
> > +++ b/arch/riscv/cpu/start.S
> > @@ -36,7 +36,7 @@
> >  .globl _start
> >  _start:
> >       /* save hart id and dtb pointer */
> > -     mv      s0, a0
> > +     mv      tp, a0
> >       mv      s1, a1
> >
> >       la      t0, trap_entry
> > @@ -64,7 +64,7 @@ call_board_init_f_0:
> >       jal     board_init_f_init_reserve
> >
> >       /* save the boot hart id to global_data */
> > -     SREG    s0, GD_BOOT_HART(gp)
> > +     SREG    tp, GD_BOOT_HART(gp)
> >
> >       /* Enable cache */
> >       jal     icache_enable

Reviewed-by: Rick Chen <rick at andestech.com>