[U-Boot] [V4 3/3] sunxi: Use clrsetbits_le32 instead of multiple instruction

[Andre Przywara]

On Mon, 18 Mar 2019 15:17:47 +0530
Shyam Saini <shyam.saini at amarulasolutions.com> wrote:

Hi,

> From: Michael Trimarchi <michael at amarulasolutions.com>
> 
> This will improve code readabilty

Somehow this patch looks horribly wrong, it doesn't even compile. See
below. Are you sure you sent the right version?

> Signed-off-by: Michael Trimarchi <michael at amarulasolutions.com>
> Signed-off-by: Shyam Saini <shyam.saini at amarulasolutions.com>
> ---
> Changelogs:
> 	   V1->V2: none
> 	   V2->V3: Fix use of clrsetbits_le32 and setbits_le32 functions
> 	   V3->V4: Rebase to original series's patch 2 and 3
> ---
>  arch/arm/mach-sunxi/dram_sun8i_a33.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> index 63e18f17d0db..9fe4c88bd87f 100644
> --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
> +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> @@ -145,11 +145,8 @@ static void auto_set_timing_para(struct dram_para *para)
>  	reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
>  	writel(reg_val, &mctl_ctl->dramtmg5);
>  	/* Set two rank timing and exit self-refresh timing */
> -	reg_val = readl(&mctl_ctl->dramtmg8);
> -	reg_val &= ~(0xff << 8);
> -	reg_val &= ~(0xff << 0);
> -	reg_val |= (0x33 << 8);
> -	reg_val |= (0x10 << 0);
> +	clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0));
> +	setbits_le32(&mctl_ctl->dramtmg8, (0x33 << 8) | (0x10 << 0));

That should just be one call to clrsetbits_le32().

>  	writel(reg_val, &mctl_ctl->dramtmg8);

And you need to remove this line, of course, otherwise you write the value of dramtmg5 into dramtmg8.

Cheers,
Andre.

>  	/* Set phy interface time */
>  	reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)