[U-Boot] [PATCH v3 03/10] pinctrl: rockchip: Split the common set_mux() into per Soc【请注意，邮件由u-boot-bounces at lists.denx.de代发】
Kever Yang
kever.yang at rock-chips.com
Thu May 9 01:25:12 UTC 2019
On 05/07/2019 11:43 AM, Kever Yang wrote:
>
> On 04/16/2019 09:50 PM, David Wu wrote:
>> Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
>> higher 16 writing corresponding bits, use common set_mux() func would
>> introduce more code, so implement their set_mux() in each Soc's own
>> file to reduce the size of code.
>>
>> Signed-off-by: David Wu <david.wu at rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang at rock-chips.com>
Applied to u-boot-rockchip, thanks!
>
> Thanks,
> - Kever
>> ---
>>
>> Change in v3:
>> - None
>>
>> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 25 +++++++++++
>> drivers/pinctrl/rockchip/pinctrl-rk3128.c | 37 +++++++++++++++++
>> drivers/pinctrl/rockchip/pinctrl-rk3188.c | 25 +++++++++++
>> drivers/pinctrl/rockchip/pinctrl-rk322x.c | 34 +++++++++++++++
>> drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +++++++++++++++-
>> drivers/pinctrl/rockchip/pinctrl-rk3328.c | 37 +++++++++++++++++
>> drivers/pinctrl/rockchip/pinctrl-rk3368.c | 25 +++++++++++
>> drivers/pinctrl/rockchip/pinctrl-rk3399.c | 34 +++++++++++++++
>> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 41 +++++--------------
>> drivers/pinctrl/rockchip/pinctrl-rockchip.h | 8 ++++
>> drivers/pinctrl/rockchip/pinctrl-rv1108.c | 28 +++++++++++++
>> 11 files changed, 297 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> index 2a651cd9b8..8969aea2e3 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> @@ -11,6 +11,30 @@
>>
>> #include "pinctrl-rockchip.h"
>>
>> +static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3036_PULL_OFFSET 0x118
>> #define RK3036_PULL_PINS_PER_REG 16
>> #define RK3036_PULL_BANK_STRIDE 8
>> @@ -41,6 +65,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
>> .label = "RK3036-GPIO",
>> .type = RK3036,
>> .grf_mux_offset = 0xa8,
>> + .set_mux = rk3036_set_mux,
>> .pull_calc_reg = rk3036_calc_pull_reg_and_bit,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> index 43a6c173a0..de203334c7 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> @@ -98,6 +98,42 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
>> },
>> };
>>
>> +static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data, route_reg, route_val;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + if (bank->recalced_mask & BIT(pin))
>> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
>> +
>> + if (bank->route_mask & BIT(pin)) {
>> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
>> + &route_val)) {
>> + ret = regmap_write(regmap, route_reg, route_val);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3128_PULL_OFFSET 0x118
>> #define RK3128_PULL_PINS_PER_REG 16
>> #define RK3128_PULL_BANK_STRIDE 8
>> @@ -133,6 +169,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
>> .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
>> .iomux_routes = rk3128_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
>> + .set_mux = rk3128_set_mux,
>> .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
>> index 7cc52c0075..617ae28ac8 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
>> @@ -11,6 +11,30 @@
>>
>> #include "pinctrl-rockchip.h"
>>
>> +static int rk3188_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3188_PULL_OFFSET 0x164
>> #define RK3188_PULL_PMU_OFFSET 0x64
>>
>> @@ -60,6 +84,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
>> .label = "RK3188-GPIO",
>> .type = RK3188,
>> .grf_mux_offset = 0x60,
>> + .set_mux = rk3188_set_mux,
>> .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> index d67b48a06a..442c40ce0b 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> @@ -141,6 +141,39 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
>> },
>> };
>>
>> +static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data, route_reg, route_val;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + if (bank->route_mask & BIT(pin)) {
>> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
>> + &route_val)) {
>> + ret = regmap_write(regmap, route_reg, route_val);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3228_PULL_OFFSET 0x100
>>
>> static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> @@ -190,6 +223,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
>> .grf_mux_offset = 0x0,
>> .iomux_routes = rk3228_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
>> + .set_mux = rk3228_set_mux,
>> .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
>> .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
>> };
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> index 3648f37207..1fa601d954 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> @@ -7,7 +7,6 @@
>> #include <dm.h>
>> #include <dm/pinctrl.h>
>> #include <regmap.h>
>> -#include <syscon.h>
>>
>> #include "pinctrl-rockchip.h"
>>
>> @@ -29,6 +28,39 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
>> },
>> };
>>
>> +static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data, route_reg, route_val;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + if (bank->route_mask & BIT(pin)) {
>> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
>> + &route_val)) {
>> + ret = regmap_write(regmap, route_reg, route_val);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3288_PULL_OFFSET 0x140
>> #define RK3288_PULL_PMU_OFFSET 0x64
>>
>> @@ -132,6 +164,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
>> .pmu_mux_offset = 0x84,
>> .iomux_routes = rk3288_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
>> + .set_mux = rk3288_set_mux,
>> .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
>> .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
>> };
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> index ab634c1123..de21fba69c 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> @@ -121,6 +121,42 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
>> },
>> };
>>
>> +static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data, route_reg, route_val;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + if (bank->recalced_mask & BIT(pin))
>> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
>> +
>> + if (bank->route_mask & BIT(pin)) {
>> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
>> + &route_val)) {
>> + ret = regmap_write(regmap, route_reg, route_val);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3328_PULL_OFFSET 0x100
>>
>> static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> @@ -201,6 +237,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
>> .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
>> .iomux_routes = rk3328_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
>> + .set_mux = rk3328_set_mux,
>> .pull_calc_reg = rk3328_calc_pull_reg_and_bit,
>> .drv_calc_reg = rk3328_calc_drv_reg_and_bit,
>> .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> index 8bdaf5e4d2..c1f692a1cf 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> @@ -11,6 +11,30 @@
>>
>> #include "pinctrl-rockchip.h"
>>
>> +static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3368_PULL_GRF_OFFSET 0x100
>> #define RK3368_PULL_PMU_OFFSET 0x10
>>
>> @@ -91,6 +115,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
>> .type = RK3368,
>> .grf_mux_offset = 0x0,
>> .pmu_mux_offset = 0x0,
>> + .set_mux = rk3368_set_mux,
>> .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
>> .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
>> };
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> index 06276b14ef..9e8dc2ef82 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> @@ -50,6 +50,39 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
>> },
>> };
>>
>> +static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data, route_reg, route_val;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + if (bank->route_mask & BIT(pin)) {
>> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
>> + &route_val)) {
>> + ret = regmap_write(regmap, route_reg, route_val);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RK3399_PULL_GRF_OFFSET 0xe040
>> #define RK3399_PULL_PMU_OFFSET 0x40
>>
>> @@ -168,6 +201,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
>> .pmu_drv_offset = 0x80,
>> .iomux_routes = rk3399_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
>> + .set_mux = rk3399_set_mux,
>> .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
>> .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
>> };
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> index 77ac981c40..355fa6c8ad 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> @@ -35,8 +35,8 @@ static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
>> return 0;
>> }
>>
>> -static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
>> - int *reg, u8 *bit, int *mask)
>> +void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
>> + int *reg, u8 *bit, int *mask)
>> {
>> struct rockchip_pinctrl_priv *priv = bank->priv;
>> struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> @@ -58,8 +58,8 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
>> *bit = data->bit;
>> }
>>
>> -static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
>> - int mux, u32 *reg, u32 *value)
>> +bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
>> + int mux, u32 *reg, u32 *value)
>> {
>> struct rockchip_pinctrl_priv *priv = bank->priv;
>> struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> @@ -82,7 +82,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
>> return true;
>> }
>>
>> -static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
>> +int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
>> {
>> int offset = 0;
>>
>> @@ -193,11 +193,9 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
>> static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> {
>> struct rockchip_pinctrl_priv *priv = bank->priv;
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> int iomux_num = (pin / 8);
>> - struct regmap *regmap;
>> - int reg, ret, mask, mux_type;
>> - u8 bit;
>> - u32 data, route_reg, route_val;
>> + int ret;
>>
>> ret = rockchip_verify_mux(bank, pin, mux);
>> if (ret < 0)
>> @@ -208,29 +206,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>>
>> debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
>>
>> - regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> - ? priv->regmap_pmu : priv->regmap_base;
>> -
>> - /* get basic quadrupel of mux registers and the correct reg inside */
>> - mux_type = bank->iomux[iomux_num].type;
>> - reg = bank->iomux[iomux_num].offset;
>> - reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> -
>> - if (bank->recalced_mask & BIT(pin))
>> - rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
>> -
>> - if (bank->route_mask & BIT(pin)) {
>> - if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
>> - &route_val)) {
>> - ret = regmap_write(regmap, route_reg, route_val);
>> - if (ret)
>> - return ret;
>> - }
>> - }
>> + if (!ctrl->set_mux)
>> + return -ENOTSUPP;
>>
>> - data = (mask << (bit + 16));
>> - data |= (mux & mask) << bit;
>> - ret = regmap_write(regmap, reg, data);
>> + ret = ctrl->set_mux(bank, pin, mux);
>>
>> return ret;
>> }
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> index bc809630c1..db89b49238 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> @@ -277,6 +277,9 @@ struct rockchip_pin_ctrl {
>> struct rockchip_mux_route_data *iomux_routes;
>> u32 niomux_routes;
>>
>> + int (*set_mux)(struct rockchip_pin_bank *bank,
>> + int pin, int mux);
>> +
>> void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
>> int pin_num, struct regmap **regmap,
>> int *reg, u8 *bit);
>> @@ -298,5 +301,10 @@ struct rockchip_pinctrl_priv {
>>
>> extern const struct pinctrl_ops rockchip_pinctrl_ops;
>> int rockchip_pinctrl_probe(struct udevice *dev);
>> +void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
>> + int *reg, u8 *bit, int *mask);
>> +bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
>> + int mux, u32 *reg, u32 *value);
>> +int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
>>
>> #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> index f4a09a6824..c28b504634 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> @@ -75,6 +75,33 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
>> },
>> };
>>
>> +static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
>> +
>> + if (bank->recalced_mask & BIT(pin))
>> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> #define RV1108_PULL_PMU_OFFSET 0x10
>> #define RV1108_PULL_OFFSET 0x110
>>
>> @@ -177,6 +204,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
>> .pmu_mux_offset = 0x0,
>> .iomux_recalced = rv1108_mux_recalced_data,
>> .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
>> + .set_mux = rv1108_set_mux,
>> .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
>> .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
>> .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
>
>
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