[U-Boot] [PATCH v3 05/10] pinctrl: rockchip: Split the common set_drive() func into per Soc【请注意,邮件由u-boot-bounces at lists.denx.de代发】

Kever Yang kever.yang at rock-chips.com
Thu May 9 01:25:37 UTC 2019



On 05/07/2019 11:43 AM, Kever Yang wrote:
>
> On 04/16/2019 09:55 PM, David Wu wrote:
>> As the common set_mux func(), implement the feature at the own file
>> for each Soc.
>>
>> Signed-off-by: David Wu <david.wu at rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Applied to u-boot-rockchip, thanks!

>
> Thanks,
> - Kever
>> ---
>>
>> Change in v3:
>> - None
>>
>>  drivers/pinctrl/rockchip/pinctrl-rk322x.c     | 25 ++++-
>>  drivers/pinctrl/rockchip/pinctrl-rk3288.c     | 35 +++++--
>>  drivers/pinctrl/rockchip/pinctrl-rk3328.c     | 26 ++++-
>>  drivers/pinctrl/rockchip/pinctrl-rk3368.c     | 36 +++++--
>>  drivers/pinctrl/rockchip/pinctrl-rk3399.c     | 75 ++++++++++++++-
>>  .../pinctrl/rockchip/pinctrl-rockchip-core.c  | 95 ++++---------------
>>  drivers/pinctrl/rockchip/pinctrl-rockchip.h   |  6 +-
>>  drivers/pinctrl/rockchip/pinctrl-rv1108.c     | 26 ++++-
>>  8 files changed, 224 insertions(+), 100 deletions(-)
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> index 442c40ce0b..10200ff3c8 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c
>> @@ -208,6 +208,29 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>>  }
>>  
>> +static int rk3228_set_drive(struct rockchip_pin_bank *bank,
>> +			    int pin_num, int strength)
>> +{
>> +	struct regmap *regmap;
>> +	int reg, ret;
>> +	u32 data;
>> +	u8 bit;
>> +	int type = bank->drv[pin_num / 8].drv_type;
>> +
>> +	rk3228_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
>> +	ret = rockchip_translate_drive_value(type, strength);
>> +	if (ret < 0) {
>> +		debug("unsupported driver strength %d\n", strength);
>> +		return ret;
>> +	}
>> +
>> +	/* enable the write to the equivalent lower bits */
>> +	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
>> +	data |= (ret << bit);
>> +	ret = regmap_write(regmap, reg, data);
>> +	return ret;
>> +}
>> +
>>  static struct rockchip_pin_bank rk3228_pin_banks[] = {
>>  	PIN_BANK(0, 32, "gpio0"),
>>  	PIN_BANK(1, 32, "gpio1"),
>> @@ -225,7 +248,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
>>  	.niomux_routes		= ARRAY_SIZE(rk3228_mux_route_data),
>>  	.set_mux		= rk3228_set_mux,
>>  	.pull_calc_reg		= rk3228_calc_pull_reg_and_bit,
>> -	.drv_calc_reg		= rk3228_calc_drv_reg_and_bit,
>> +	.set_drive		= rk3228_set_drive,
>>  };
>>  
>>  static const struct udevice_id rk3228_pinctrl_ids[] = {
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> index 5040cd8f48..6ae9f1c76e 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
>> @@ -113,10 +113,6 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  	if (bank->bank_num == 0) {
>>  		*regmap = priv->regmap_pmu;
>>  		*reg = RK3288_DRV_PMU_OFFSET;
>> -
>> -		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
>> -		*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
>> -		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>>  	} else {
>>  		*regmap = priv->regmap_base;
>>  		*reg = RK3288_DRV_GRF_OFFSET;
>> @@ -124,11 +120,34 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  		/* correct the offset, as we're starting with the 2nd bank */
>>  		*reg -= 0x10;
>>  		*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
>> -		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
>> +	}
>> +
>> +	*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
>> +	*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
>> +	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>> +}
>>  
>> -		*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
>> -		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>> +static int rk3288_set_drive(struct rockchip_pin_bank *bank,
>> +			    int pin_num, int strength)
>> +{
>> +	struct regmap *regmap;
>> +	int reg, ret;
>> +	u32 data;
>> +	u8 bit;
>> +	int type = bank->drv[pin_num / 8].drv_type;
>> +
>> +	rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
>> +	ret = rockchip_translate_drive_value(type, strength);
>> +	if (ret < 0) {
>> +		debug("unsupported driver strength %d\n", strength);
>> +		return ret;
>>  	}
>> +
>> +	/* enable the write to the equivalent lower bits */
>> +	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
>> +	data |= (ret << bit);
>> +	ret = regmap_write(regmap, reg, data);
>> +	return ret;
>>  }
>>  
>>  static struct rockchip_pin_bank rk3288_pin_banks[] = {
>> @@ -174,7 +193,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
>>  	.niomux_routes		= ARRAY_SIZE(rk3288_mux_route_data),
>>  	.set_mux		= rk3288_set_mux,
>>  	.pull_calc_reg		= rk3288_calc_pull_reg_and_bit,
>> -	.drv_calc_reg		= rk3288_calc_drv_reg_and_bit,
>> +	.set_drive		= rk3288_set_drive,
>>  };
>>  
>>  static const struct udevice_id rk3288_pinctrl_ids[] = {
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> index de21fba69c..0ad5669d26 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
>> @@ -191,6 +191,30 @@ static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>>  }
>>  
>> +static int rk3328_set_drive(struct rockchip_pin_bank *bank,
>> +			    int pin_num, int strength)
>> +{
>> +	struct regmap *regmap;
>> +	int reg, ret;
>> +	u32 data;
>> +	u8 bit;
>> +	int type = bank->drv[pin_num / 8].drv_type;
>> +
>> +	rk3328_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
>> +	ret = rockchip_translate_drive_value(type, strength);
>> +	if (ret < 0) {
>> +		debug("unsupported driver strength %d\n", strength);
>> +		return ret;
>> +	}
>> +
>> +	/* enable the write to the equivalent lower bits */
>> +	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
>> +	data |= (ret << bit);
>> +	ret = regmap_write(regmap, reg, data);
>> +
>> +	return ret;
>> +}
>> +
>>  #define RK3328_SCHMITT_BITS_PER_PIN		1
>>  #define RK3328_SCHMITT_PINS_PER_REG		16
>>  #define RK3328_SCHMITT_BANK_STRIDE		8
>> @@ -239,7 +263,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
>>  	.niomux_routes		= ARRAY_SIZE(rk3328_mux_route_data),
>>  	.set_mux		= rk3328_set_mux,
>>  	.pull_calc_reg		= rk3328_calc_pull_reg_and_bit,
>> -	.drv_calc_reg		= rk3328_calc_drv_reg_and_bit,
>> +	.set_drive		= rk3328_set_drive,
>>  	.schmitt_calc_reg	= rk3328_calc_schmitt_reg_and_bit,
>>  };
>>  
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> index c1f692a1cf..40cc846fa8 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
>> @@ -79,10 +79,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  	if (bank->bank_num == 0) {
>>  		*regmap = priv->regmap_pmu;
>>  		*reg = RK3368_DRV_PMU_OFFSET;
>> -
>> -		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
>> -		*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
>> -		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>>  	} else {
>>  		*regmap = priv->regmap_base;
>>  		*reg = RK3368_DRV_GRF_OFFSET;
>> @@ -90,11 +86,35 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  		/* correct the offset, as we're starting with the 2nd bank */
>>  		*reg -= 0x10;
>>  		*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
>> -		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
>> +	}
>> +
>> +	*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
>> +	*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
>> +	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>> +}
>>  
>> -		*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
>> -		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>> +static int rk3368_set_drive(struct rockchip_pin_bank *bank,
>> +			    int pin_num, int strength)
>> +{
>> +	struct regmap *regmap;
>> +	int reg, ret;
>> +	u32 data;
>> +	u8 bit;
>> +	int type = bank->drv[pin_num / 8].drv_type;
>> +
>> +	rk3368_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
>> +	ret = rockchip_translate_drive_value(type, strength);
>> +	if (ret < 0) {
>> +		debug("unsupported driver strength %d\n", strength);
>> +		return ret;
>>  	}
>> +
>> +	/* enable the write to the equivalent lower bits */
>> +	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
>> +	data |= (ret << bit);
>> +	ret = regmap_write(regmap, reg, data);
>> +
>> +	return ret;
>>  }
>>  
>>  static struct rockchip_pin_bank rk3368_pin_banks[] = {
>> @@ -117,7 +137,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
>>  	.pmu_mux_offset		= 0x0,
>>  	.set_mux		= rk3368_set_mux,
>>  	.pull_calc_reg		= rk3368_calc_pull_reg_and_bit,
>> -	.drv_calc_reg		= rk3368_calc_drv_reg_and_bit,
>> +	.set_drive		= rk3368_set_drive,
>>  };
>>  
>>  static const struct udevice_id rk3368_pinctrl_ids[] = {
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> index 9e8dc2ef82..82c8feeb7b 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c
>> @@ -137,6 +137,79 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  		*bit = (pin_num % 8) * 2;
>>  }
>>  
>> +static int rk3399_set_drive(struct rockchip_pin_bank *bank,
>> +			    int pin_num, int strength)
>> +{
>> +	struct regmap *regmap;
>> +	int reg, ret;
>> +	u32 data, rmask_bits, temp;
>> +	u8 bit;
>> +	int drv_type = bank->drv[pin_num / 8].drv_type;
>> +
>> +	rk3399_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
>> +	ret = rockchip_translate_drive_value(drv_type, strength);
>> +	if (ret < 0) {
>> +		debug("unsupported driver strength %d\n", strength);
>> +		return ret;
>> +	}
>> +
>> +	switch (drv_type) {
>> +	case DRV_TYPE_IO_1V8_3V0_AUTO:
>> +	case DRV_TYPE_IO_3V3_ONLY:
>> +		rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
>> +		switch (bit) {
>> +		case 0 ... 12:
>> +			/* regular case, nothing to do */
>> +			break;
>> +		case 15:
>> +			/*
>> +			 * drive-strength offset is special, as it is spread
>> +			 * over 2 registers, the bit data[15] contains bit 0
>> +			 * of the value while temp[1:0] contains bits 2 and 1
>> +			 */
>> +			data = (ret & 0x1) << 15;
>> +			temp = (ret >> 0x1) & 0x3;
>> +
>> +			data |= BIT(31);
>> +			ret = regmap_write(regmap, reg, data);
>> +			if (ret)
>> +				return ret;
>> +
>> +			temp |= (0x3 << 16);
>> +			reg += 0x4;
>> +			ret = regmap_write(regmap, reg, temp);
>> +
>> +			return ret;
>> +		case 18 ... 21:
>> +			/* setting fully enclosed in the second register */
>> +			reg += 4;
>> +			bit -= 16;
>> +			break;
>> +		default:
>> +			debug("unsupported bit: %d for pinctrl drive type: %d\n",
>> +			      bit, drv_type);
>> +			return -EINVAL;
>> +		}
>> +		break;
>> +	case DRV_TYPE_IO_DEFAULT:
>> +	case DRV_TYPE_IO_1V8_OR_3V0:
>> +	case DRV_TYPE_IO_1V8_ONLY:
>> +		rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
>> +		break;
>> +	default:
>> +		debug("unsupported pinctrl drive type: %d\n",
>> +		      drv_type);
>> +		return -EINVAL;
>> +	}
>> +
>> +	/* enable the write to the equivalent lower bits */
>> +	data = ((1 << rmask_bits) - 1) << (bit + 16);
>> +	data |= (ret << bit);
>> +	ret = regmap_write(regmap, reg, data);
>> +
>> +	return ret;
>> +}
>> +
>>  static struct rockchip_pin_bank rk3399_pin_banks[] = {
>>  	PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
>>  							 IOMUX_SOURCE_PMU,
>> @@ -203,7 +276,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
>>  	.niomux_routes		= ARRAY_SIZE(rk3399_mux_route_data),
>>  	.set_mux		= rk3399_set_mux,
>>  	.pull_calc_reg		= rk3399_calc_pull_reg_and_bit,
>> -	.drv_calc_reg		= rk3399_calc_drv_reg_and_bit,
>> +	.set_drive		= rk3399_set_drive,
>>  };
>>  
>>  static const struct udevice_id rk3399_pinctrl_ids[] = {
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> index 355fa6c8ad..439e8ba1b5 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
>> @@ -222,93 +222,37 @@ static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
>>  	{ 4, 7, 10, 13, 16, 19, 22, 26 }
>>  };
>>  
>> -static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
>> -				     int pin_num, int strength)
>> +int rockchip_translate_drive_value(int type, int strength)
>>  {
>> -	struct rockchip_pinctrl_priv *priv = bank->priv;
>> -	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> -	struct regmap *regmap;
>> -	int reg, ret, i;
>> -	u32 data, rmask_bits, temp;
>> -	u8 bit;
>> -	int drv_type = bank->drv[pin_num / 8].drv_type;
>> -
>> -	debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
>> -	      pin_num, strength);
>> -
>> -	ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
>> +	int i, ret;
>>  
>>  	ret = -EINVAL;
>> -	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
>> -		if (rockchip_perpin_drv_list[drv_type][i] == strength) {
>> +	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
>> +		if (rockchip_perpin_drv_list[type][i] == strength) {
>>  			ret = i;
>>  			break;
>> -		} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
>> -			ret = rockchip_perpin_drv_list[drv_type][i];
>> +		} else if (rockchip_perpin_drv_list[type][i] < 0) {
>> +			ret = rockchip_perpin_drv_list[type][i];
>>  			break;
>>  		}
>>  	}
>>  
>> -	if (ret < 0) {
>> -		debug("unsupported driver strength %d\n", strength);
>> -		return ret;
>> -	}
>> -
>> -	switch (drv_type) {
>> -	case DRV_TYPE_IO_1V8_3V0_AUTO:
>> -	case DRV_TYPE_IO_3V3_ONLY:
>> -		rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
>> -		switch (bit) {
>> -		case 0 ... 12:
>> -			/* regular case, nothing to do */
>> -			break;
>> -		case 15:
>> -			/*
>> -			 * drive-strength offset is special, as it is spread
>> -			 * over 2 registers, the bit data[15] contains bit 0
>> -			 * of the value while temp[1:0] contains bits 2 and 1
>> -			 */
>> -			data = (ret & 0x1) << 15;
>> -			temp = (ret >> 0x1) & 0x3;
>> -
>> -			data |= BIT(31);
>> -			ret = regmap_write(regmap, reg, data);
>> -			if (ret)
>> -				return ret;
>> +	return ret;
>> +}
>>  
>> -			temp |= (0x3 << 16);
>> -			reg += 0x4;
>> -			ret = regmap_write(regmap, reg, temp);
>> +static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
>> +				     int pin_num, int strength)
>> +{
>> +	struct rockchip_pinctrl_priv *priv = bank->priv;
>> +	struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>>  
>> -			return ret;
>> -		case 18 ... 21:
>> -			/* setting fully enclosed in the second register */
>> -			reg += 4;
>> -			bit -= 16;
>> -			break;
>> -		default:
>> -			debug("unsupported bit: %d for pinctrl drive type: %d\n",
>> -			      bit, drv_type);
>> -			return -EINVAL;
>> -		}
>> -		break;
>> -	case DRV_TYPE_IO_DEFAULT:
>> -	case DRV_TYPE_IO_1V8_OR_3V0:
>> -	case DRV_TYPE_IO_1V8_ONLY:
>> -		rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
>> -		break;
>> -	default:
>> -		debug("unsupported pinctrl drive type: %d\n",
>> -		      drv_type);
>> -		return -EINVAL;
>> -	}
>> +	debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
>> +	      pin_num, strength);
>>  
>> -	/* enable the write to the equivalent lower bits */
>> -	data = ((1 << rmask_bits) - 1) << (bit + 16);
>> -	data |= (ret << bit);
>> +	if (!ctrl->set_drive)
>> +		return -ENOTSUPP;
>>  
>> -	ret = regmap_write(regmap, reg, data);
>> -	return ret;
>> +	return ctrl->set_drive(bank, pin_num, strength);
>>  }
>>  
>>  static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
>> @@ -459,9 +403,6 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
>>  		break;
>>  
>>  	case PIN_CONFIG_DRIVE_STRENGTH:
>> -		if (!ctrl->drv_calc_reg)
>> -			return -ENOTSUPP;
>> -
>>  		rc = rockchip_set_drive_perpin(bank, pin, arg);
>>  		if (rc < 0)
>>  			return rc;
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> index db89b49238..2ef24dce6c 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
>> @@ -283,9 +283,8 @@ struct rockchip_pin_ctrl {
>>  	void	(*pull_calc_reg)(struct rockchip_pin_bank *bank,
>>  				 int pin_num, struct regmap **regmap,
>>  				 int *reg, u8 *bit);
>> -	void	(*drv_calc_reg)(struct rockchip_pin_bank *bank,
>> -				int pin_num, struct regmap **regmap,
>> -				int *reg, u8 *bit);
>> +	int	(*set_drive)(struct rockchip_pin_bank *bank,
>> +			     int pin_num, int strength);
>>  	int	(*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
>>  				    int pin_num, struct regmap **regmap,
>>  				    int *reg, u8 *bit);
>> @@ -306,5 +305,6 @@ void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
>>  bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
>>  			    int mux, u32 *reg, u32 *value);
>>  int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
>> +int rockchip_translate_drive_value(int type, int strength);
>>  
>>  #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> index c28b504634..1a150ff0f1 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c
>> @@ -155,6 +155,30 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>>  	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
>>  }
>>  
>> +static int rv1108_set_drive(struct rockchip_pin_bank *bank,
>> +			    int pin_num, int strength)
>> +{
>> +	struct regmap *regmap;
>> +	int reg, ret;
>> +	u32 data;
>> +	u8 bit;
>> +	int type = bank->drv[pin_num / 8].drv_type;
>> +
>> +	rv1108_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
>> +	ret = rockchip_translate_drive_value(type, strength);
>> +	if (ret < 0) {
>> +		debug("unsupported driver strength %d\n", strength);
>> +		return ret;
>> +	}
>> +
>> +	/* enable the write to the equivalent lower bits */
>> +	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
>> +
>> +	data |= (ret << bit);
>> +	ret = regmap_write(regmap, reg, data);
>> +	return ret;
>> +}
>> +
>>  #define RV1108_SCHMITT_PMU_OFFSET		0x30
>>  #define RV1108_SCHMITT_GRF_OFFSET		0x388
>>  #define RV1108_SCHMITT_BANK_STRIDE		8
>> @@ -206,7 +230,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
>>  	.niomux_recalced	= ARRAY_SIZE(rv1108_mux_recalced_data),
>>  	.set_mux		= rv1108_set_mux,
>>  	.pull_calc_reg		= rv1108_calc_pull_reg_and_bit,
>> -	.drv_calc_reg		= rv1108_calc_drv_reg_and_bit,
>> +	.set_drive		= rv1108_set_drive,
>>  	.schmitt_calc_reg	= rv1108_calc_schmitt_reg_and_bit,
>>  };
>>  
>
>
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