[U-Boot] [PATCH 2/2] ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5

[Tan, Ley Foon]

> -----Original Message-----
> From: Marek Vasut <marex at denx.de>
> Sent: Thursday, November 21, 2019 5:35 AM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex at denx.de>; See, Chin Liang
> <chin.liang.see at intel.com>; Dalon Westergreen <dwesterg at gmail.com>;
> Dinh Nguyen <dinguyen at kernel.org>; Tan, Ley Foon
> <ley.foon.tan at intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>
> Subject: [PATCH 2/2] ARM: socfpga: Purge pending transactions upon
> enabling bridges on Gen5
> 
> On Gen5, when the FPGA is loaded and there was some prior interaction
> between the HPS and the FPGA via bridges (e.g. Linux was running and using
> some of the IPs in the FPGA) followed by warm reset, it has been observed
> that there might be outstanding unfinished transactions. This leads to an
> obscure misbehavior of the bridge.
> 
> When the bridge is enabled again in U-Boot and there are outstanding
> transactions, a read from within the bridge address range would return a
> result of the previous read instead. Example:
> => bridge enable ; md 0xff200000 1
> ff200000: 1234abcd
> => bridge enable ; md 0xff200010 1
> ff200010: 5678dcba <------- this is in fact a value which is stored in
>                             a memory at 0xff200000 => bridge enable ; md 0xff200000 1
> ff200000: 90effe09 <------- this is in fact a value which is stored in
>                             a memory at 0xff200010 and so it continues. Issuing a write
> does lock the system up completely.
> 
> This patch opens the FPGA bridges in 'bridge enable' command, the tears
> them down again, and then opens them again. This allows these outstanding
> transactions to complete and makes this misbehavior go away.
> 
> However, it is not entirely clear whether this is the correct solution.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Chin Liang See <chin.liang.see at intel.com>
> Cc: Dalon Westergreen <dwesterg at gmail.com>
> Cc: Dinh Nguyen <dinguyen at kernel.org>
> Cc: Ley Foon Tan <ley.foon.tan at intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee at intel.com>

Reviewed-by: Ley Foon Tan <ley.foon.tan at intel.com>

Regards
Ley Foon