[U-Boot] [PATCH 2/2] ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5

Marek Vasut marex at denx.de
Thu Nov 21 10:17:34 UTC 2019


On 11/21/19 10:59 AM, Tan, Ley Foon wrote:
[...]

Hi,

>> Subject: [PATCH 2/2] ARM: socfpga: Purge pending transactions upon
>> enabling bridges on Gen5
>>
>> On Gen5, when the FPGA is loaded and there was some prior interaction
>> between the HPS and the FPGA via bridges (e.g. Linux was running and using
>> some of the IPs in the FPGA) followed by warm reset, it has been observed
>> that there might be outstanding unfinished transactions. This leads to an
>> obscure misbehavior of the bridge.
>>
>> When the bridge is enabled again in U-Boot and there are outstanding
>> transactions, a read from within the bridge address range would return a
>> result of the previous read instead. Example:
>> => bridge enable ; md 0xff200000 1
>> ff200000: 1234abcd
>> => bridge enable ; md 0xff200010 1
>> ff200010: 5678dcba <------- this is in fact a value which is stored in
>>                             a memory at 0xff200000 => bridge enable ; md 0xff200000 1
>> ff200000: 90effe09 <------- this is in fact a value which is stored in
>>                             a memory at 0xff200010 and so it continues. Issuing a write
>> does lock the system up completely.
>>
>> This patch opens the FPGA bridges in 'bridge enable' command, the tears
>> them down again, and then opens them again. This allows these outstanding
>> transactions to complete and makes this misbehavior go away.
>>
>> However, it is not entirely clear whether this is the correct solution.
>>
>> Signed-off-by: Marek Vasut <marex at denx.de>
>> Cc: Chin Liang See <chin.liang.see at intel.com>
>> Cc: Dalon Westergreen <dwesterg at gmail.com>
>> Cc: Dinh Nguyen <dinguyen at kernel.org>
>> Cc: Ley Foon Tan <ley.foon.tan at intel.com>
>> Cc: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
>> Cc: Tien Fong Chee <tien.fong.chee at intel.com>
> 
> Reviewed-by: Ley Foon Tan <ley.foon.tan at intel.com>

Do you think there is anyone still at Altera/intel who might be able to
tell us what this problem really is about ? And whether there is some
way to purge those stuck transactions without turning the bridges on and
off and then on again ? Or whether there is a way to even verify there
are stuck transactions ?

-- 
Best regards,
Marek Vasut


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