[PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images

[Tan, Ley Foon]

> -----Original Message-----
> From: Marek Vasut <marex at denx.de>
> Sent: Wednesday, August 5, 2020 5:18 PM
> To: Tan, Ley Foon <ley.foon.tan at intel.com>; Ang, Chee Hong
> <chee.hong.ang at intel.com>; u-boot at lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Tom Rini
> <trini at konsulko.com>; See, Chin Liang <chin.liang.see at intel.com>; Chee,
> Tien Fong <tien.fong.chee at intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim at intel.com>
> Subject: Re: [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp
> with 4 SPL images
> 
> On 8/5/20 11:15 AM, Tan, Ley Foon wrote:
> [...]
> >>> diff --git a/Makefile b/Makefile
> >>> index 2629a74..13429a0 100644
> >>> --- a/Makefile
> >>> +++ b/Makefile
> >>> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
> >> FORCE
> >>> ifneq ($(CONFIG_ARCH_SOCFPGA),)  quiet_cmd_socboot = SOCBOOT
> $@
> >>>  cmd_socboot = cat	spl/u-boot-spl.sfp spl/u-boot-spl.sfp	\
> >>> -			spl/u-boot-spl.sfp spl/u-boot-spl.sfp	\
> >>> -			u-boot.img > $@ || rm -f $@
> >>> +			spl/u-boot-spl.sfp \
> >>> +			spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> >>> +	      cat	spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
> >>
> >> Isn't that what the existing code does already ?
> >>
> >> Also, this will I think fail on 128k erase block size NAND due to
> >> missing padding.
> > This is to generate an output file (spl/u-boot-splx4.sfp) with 4 SPL images,
> each SPL image size is 256KB.
> > So, spl/u-boot-splx4.sfp is always with 1MB size (4x256KB). Shouldn't have
> problem for 128KB erase size NAND.
> 
> Isn't the SPL padded to 64 kiB each ?
Cyclone 5 and Arria 10 have different size.

Cyclone 5 SPL: 64KB each, spl/u-boot-splx4.sfp is 256KB

Arria 10 SPL: 256KB each, spl/u-boot-splx4.sfp is 1MB

Regards
Ley Foon