[PATCH v2 00/10] riscv: Add SPI support for Kendryte K210

Sean Anderson seanga2 at gmail.com
Fri Aug 7 16:43:07 CEST 2020

This series adds support for SPI on the Kendryte K210. This covers the MMC
slot (currently broken) and SPI flash on the Sipeed Maix Bit.

This series makes significant changes to the designware SPI driver. I would
really appreciate if the maintainers I CC'd could test this series and
ensure that SPI still works on all their devices. I have tried my best not
to affect existing devices, but I'd rather find out if this breaks stuff
now rather than later.

In particular:

Ley Foon Tan, can you try using dw_spi_dw32_init with the Stratix 10 and
Agilex SoCFPGAs? From their documentation, it is unclear whether one should
use the DFS or DFS_32 field. I have used dw_spi_dw16_init for these
devices, since that keeps the same behavior as before this series, but I am
interested in seeing whether the DFS_32 works.

Gregory Clement, Lars Povlsen, and Horatiu Vultur, can you confirm the
register layout of ctrlr0 and version of the device on the MSCC Ocelot and
Jaguar 2? I couldn't find any documentation for the device on those SoCs

Alexey Brodkin and Eugeniy Paltsev, can you confirm the register layout of
ctrlr0 and version of the device on ARC SoCs? I couldn't find any
documentation for the device on those SoCs online. In addition, can you
clarify the nature of SSI_MAX_XFER_SIZE? Is it set once before the device
is fabricated, or is it set at runtime? Is there any way to detect it at
runtime? Is my supposition that it was introduced in version 3.23 correct?
Have there been any other breaking changes which I have overlooked? I tried
investigating some of this, but I was unable to find any definitive ruling
on the matter. All I could find was this forum post which doesn't really
explain anything [1].

[1] https://community.intel.com/t5/Intel-Makers/D2000-SPI-word-frame-size/td-p/276520

This series was previously part of

This series depends on

Known bugs:
- The MMC cannot be accessed with the dw_spi driver

Changes in v2:
- Add Gigadevice SPI chips to dependencies
- Add external gpio cs support
- Clean up exec_op
- Configure ctrlr0 register layout based on compatible string
- Convert debug calls to log_ instead of removing the ones which affect
- Document new compatible strings
- Limit data transfers to 64k
- Remove broken-wp property (implicit due to no wp gpio)
- Remove ctrl0 field offsets from device tree
- Switch to new compatible strings
- Switch to new pinmux binding style

Sean Anderson (10):
  spi: dw: Convert calls to debug to log_*
  spi: dw: Rename "cs-gpio" to "cs-gpios"
  spi: dw: Use generic function to read reg address
  spi: dw: Rearrange struct dw_spi_priv
  spi: dw: Add SoC-specific compatible strings
  spi: dw: Configure ctrlr0 layout based on compatible string
  spi: dw: Document devicetree binding
  spi: dw: Add mem_ops
  riscv: Add device tree bindings for SPI
  riscv: Add support for SPI on Kendryte K210

 arch/arc/dts/axs10x_mb.dtsi                   |   5 +-
 arch/arc/dts/hsdk-common.dtsi                 |   5 +-
 arch/arm/dts/socfpga.dtsi                     |   6 +-
 arch/arm/dts/socfpga_agilex.dtsi              |   6 +-
 arch/arm/dts/socfpga_arria10.dtsi             |   6 +-
 arch/arm/dts/socfpga_stratix10.dtsi           |   6 +-
 arch/mips/dts/mscc,jr2.dtsi                   |   2 +-
 arch/mips/dts/mscc,ocelot.dtsi                |   2 +-
 arch/riscv/dts/k210-maix-bit.dts              |  46 ++-
 arch/riscv/dts/k210.dtsi                      |  15 +-
 board/sipeed/maix/Kconfig                     |  11 +
 configs/sipeed_maix_bitm_defconfig            |   8 +
 doc/board/sipeed/maix.rst                     |  94 +++--
 .../spi/snps,dw-apb-ssi.txt                   |  56 +++
 drivers/spi/designware_spi.c                  | 381 ++++++++++++++----
 15 files changed, 528 insertions(+), 121 deletions(-)
 create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt


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