xypron.glpk at gmx.de
Sun Aug 9 21:16:03 CEST 2020
Am 9. August 2020 18:35:45 MESZ schrieb Sean Anderson <seanga2 at gmail.com>:
>On 8/9/20 12:14 PM, Heinrich Schuchardt wrote:
>> Hello Sean,
>> while trying to understand the handling of SMP I stumbled of this
>> Why did you define CONFIG_SYS_INIT_SP_ADDR as an odd number on the
>> in commit a7c81fc85326 ("riscv: Add Sipeed Maix support") while the
>> other RISC-V boards use an even number:
>> 29 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE +
>> 22 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE +
>> 13 | #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
>> I always thought that RISC-V stack pointers must be 16 byte aligned:
>> Cf. https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf
>> "In the standard RISC-V calling convention, the stack grows downward
>> the stack pointer is always kept 16-byte aligned."
>Because that is the top of (non-ai) ram. And it gets 16-byte aligned by
Top of RAM is the place to which we want to relocate U-Boot. But furthermore this value minus a multiple of16KiB is also used for the stack lication of the secondary CPU.
Shouldn't we better use the same definition as the other boards?
More information about the U-Boot