[PATCH] arm: socfpga: soc64: Document down boot_scratch_cold register usage

[Lim, Elly Siew Chin]

Kindly ignore this patch review request. There is one more comment need to be added for SYSMGR_SOC64_BOOT_SCRATCH_COLD3 register. I will send "PATCH v2" for review. 

Thanks a lot,
Siew Chin


-----Original Message-----
From: Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com> 
Sent: Monday, August 10, 2020 10:05 AM
To: u-boot at lists.denx.de
Cc: Marek Vasut <marex at denx.de>; Ley Foon Tan <lftan.linux at gmail.com>; See, Chin Liang <chin.liang.see at intel.com>; Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Ang, Chee Hong <chee.hong.ang at intel.com>; Chee, Tien Fong <tien.fong.chee at intel.com>; Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com>
Subject: [PATCH] arm: socfpga: soc64: Document down boot_scratch_cold register usage

From: Chin Liang See <chin.liang.see at intel.com>

Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux.

Signed-off-by: Chin Liang See <chin.liang.see at intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim at intel.com>
---
 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c90f63a754..0b0eb7a259 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -46,13 +46,20 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
 #define SYSMGR_SOC64_GPO			0xe4
 #define SYSMGR_SOC64_GPI			0xe8
 #define SYSMGR_SOC64_MPU			0xf0
+/* store qspi ref clock */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0		0x200
+/* store osc1 clock freq */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1		0x204
+/* store fpga clock freq */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD2		0x208
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD3		0x20c
+/* store PSCI_CPU_ON value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD4		0x210
+/* store PSCI_CPU_ON value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD5		0x214
+/* store VBAR_EL3 value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6		0x218
+/* store VBAR_EL3 value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7		0x21c
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8		0x220
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9		0x224
--
2.19.0