[PATCH v2 23/25] watchdog: Add reset support for OcteonTX / TX2

[Stefan Roese]

From: Suneel Garapati <sgarapati at marvell.com>

Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.

Signed-off-by: Suneel Garapati <sgarapati at marvell.com>
Signed-off-by: Stefan Roese <sr at denx.de>
Reviewed-by: Simon Glass <sjg at chromium.org>

---

Changes in v2:
- Add Reviewed-by tag from Simon
- Add CORE0_POKE_OFFSET_MASK and calculate poke register address in
  _probe() instead of repeatedly in _reset()
- Slightly change the Kconfig entry: use "default y", it already depends
  on "WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)"

Changes in v1:
- Change patch subject
- Remove inclusion of common.h
- Remove global wdt_dev as its unused
- Remove #ifdef's
- Remove optional fixed register access - only use address passed via
  DT while probing
- Use dev_remap_addr() instead of dev_read_addr_index()

 drivers/watchdog/Kconfig        | 10 +++++
 drivers/watchdog/Makefile       |  1 +
 drivers/watchdog/octeontx_wdt.c | 66 +++++++++++++++++++++++++++++++++
 3 files changed, 77 insertions(+)
 create mode 100644 drivers/watchdog/octeontx_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0ebf116b12..210d9f8093 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -139,6 +139,16 @@ config WDT_MTK
 	  The watchdog timer is stopped when initialized.
 	  It performs full SoC reset.
 
+config WDT_OCTEONTX
+	bool "OcteonTX core watchdog support"
+	depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+	default y
+	imply WATCHDOG
+	help
+	  This enables OcteonTX watchdog driver, which can be
+	  found on OcteonTX/TX2 chipsets and inline with driver model.
+	  Only supports watchdog reset.
+
 config WDT_OMAP3
 	bool "TI OMAP watchdog timer support"
 	depends on WDT && ARCH_OMAP2PLUS
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 111e258195..01b8231f2b 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
 obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
 obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
 obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
 obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
 obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
 obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
new file mode 100644
index 0000000000..1e0670e0c5
--- /dev/null
+++ b/drivers/watchdog/octeontx_wdt.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <wdt.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CORE0_POKE_OFFSET	0x50000
+#define CORE0_POKE_OFFSET_MASK	0xfffffULL
+
+struct octeontx_wdt {
+	void __iomem *reg;
+};
+
+static int octeontx_wdt_reset(struct udevice *dev)
+{
+	struct octeontx_wdt *priv = dev_get_priv(dev);
+
+	writeq(~0ULL, priv->reg);
+
+	return 0;
+}
+
+static int octeontx_wdt_probe(struct udevice *dev)
+{
+	struct octeontx_wdt *priv = dev_get_priv(dev);
+
+	priv->reg = dev_remap_addr(dev);
+	if (!priv->reg)
+		return -EINVAL;
+
+	/*
+	 * Save core poke register address in reg (its not 0xa0000 as
+	 * extracted from the DT but 0x50000 instead)
+	 */
+	priv->reg = (void __iomem *)(((u64)priv->reg &
+				      ~CORE0_POKE_OFFSET_MASK) |
+				     CORE0_POKE_OFFSET);
+
+	return 0;
+}
+
+static const struct wdt_ops octeontx_wdt_ops = {
+	.reset = octeontx_wdt_reset,
+};
+
+static const struct udevice_id octeontx_wdt_ids[] = {
+	{ .compatible = "arm,sbsa-gwdt" },
+	{}
+};
+
+U_BOOT_DRIVER(wdt_octeontx) = {
+	.name = "wdt_octeontx",
+	.id = UCLASS_WDT,
+	.of_match = octeontx_wdt_ids,
+	.ops = &octeontx_wdt_ops,
+	.priv_auto_alloc_size = sizeof(struct octeontx_wdt),
+	.probe = octeontx_wdt_probe,
+};
-- 
2.28.0