[PATCH v3 06/11] clk: mt7622: add needed clocks for ssusb-node

[Frank Wunderlich]

From: Frank Wunderlich <frank-w at public-files.de>

MT7622 needs additional clock definitions to work properly

Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
---
 drivers/clk/mediatek/clk-mt7622.c | 43 ++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index d53ed69189..0246149107 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
 	.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
 }
 
+static const struct mtk_gate_regs ssusb_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x30,
+	.sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) {                      \
+	.id = _id,                                              \
+	.parent = _parent,                                      \
+	.regs = &ssusb_cg_regs,                                 \
+	.shift = _shift,                                        \
+	.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
+}
+
 static const struct mtk_gate sgmii_cgs[] = {
 	GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
 	GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
@@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
 	GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
 };
 
+static const struct mtk_gate ssusb_cgs[] = {
+	GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+	GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+	GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+	GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+	GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
+	GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
+};
+
 static const struct mtk_clk_tree mt7622_clk_tree = {
 	.xtal_rate = 25 * MHZ,
 	.xtal2_rate = 25 * MHZ,
@@ -599,7 +622,6 @@ static int mt7622_pciesys_bind(struct udevice *dev)
 	int ret = 0;
 
 	if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
-//	PCIESYS uses in linux also 0x34 = ETHSYS reset controller
 	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
 	if (ret)
 		debug("Warning: failed to bind reset controller\n");
@@ -631,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
 	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
 }
 
+static int mt7622_ssusbsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
+}
+
 static const struct udevice_id mt7622_apmixed_compat[] = {
 	{ .compatible = "mediatek,mt7622-apmixedsys" },
 	{ }
@@ -671,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
 	{ }
 };
 
+static const struct udevice_id mt7622_ssusbsys_compat[] = {
+	{ .compatible = "mediatek,mt7622-ssusbsys" },
+	{ }
+};
+
 U_BOOT_DRIVER(mtk_mcucfg) = {
 	.name = "mt7622-mcucfg",
 	.id = UCLASS_SYSCON,
@@ -747,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
 	.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 	.ops = &mtk_clk_gate_ops,
 };
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+	.name = "mt7622-clock-ssusbsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_ssusbsys_compat,
+	.probe = mt7622_ssusbsys_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
-- 
2.25.1