[PATCH] armv8: lx2162aqds: Add support for LX2162AQDS platform
meenakshi.aggarwal at nxp.com
meenakshi.aggarwal at nxp.com
Tue Aug 25 10:09:45 CEST 2020
From: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
This patch add base support for LX2162 QDS board.
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
Board support's 4GB ddr memory, i2c, micro-click module, microSD card,
serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
interface,one usb 3.0 and serdes interface to support three x1gen3
pcie interface.
Signed-off-by: Ioana Ciornei <ioana.ciornei at nxp.com>
Signed-off-by: Zhao Qiang <qiang.zhao at nxp.com>
Signed-off-by: hui.song <hui.song_1 at nxp.com>
Signed-off-by: Manish Tomar <manish.tomar at nxp.com>
Signed-off-by: Vikas Singh <vikas.singh at nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
---
arch/arm/Kconfig | 12 +
arch/arm/cpu/armv8/Kconfig | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 +-
arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +-
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-lx2162a-qds.dts | 107 +++
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 5 +-
board/freescale/lx2160a/Kconfig | 16 +
board/freescale/lx2160a/MAINTAINERS | 14 +-
board/freescale/lx2160a/Makefile | 1 +
board/freescale/lx2160a/eth_lx2162aqds.c | 849 +++++++++++++++++++++
board/freescale/lx2160a/lx2160a.c | 42 +-
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 83 ++
configs/lx2162aqds_tfa_defconfig | 83 ++
configs/lx2162aqds_tfa_verified_boot_defconfig | 93 +++
drivers/pci/pcie_layerscape.c | 4 +-
drivers/pci/pcie_layerscape_fixup_common.c | 5 +-
include/configs/lx2160a_common.h | 2 +
include/configs/lx2160aqds.h | 2 +-
include/configs/lx2160ardb.h | 2 +-
include/configs/lx2162aqds.h | 175 +++++
21 files changed, 1494 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts
create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c
create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/lx2162aqds_tfa_defconfig
create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig
create mode 100644 include/configs/lx2162aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bbb1e27..492224f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1244,6 +1244,18 @@ config TARGET_LX2160AQDS
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2162AQDS
+ bool "Support lx2162aqds"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2162AQDS platform.
+ The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 16c83e8..a4fec59 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -109,7 +109,7 @@ config PSCI_RESET
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
- !TARGET_LX2160AQDS && \
+ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b443894..25449d0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@@ -75,6 +75,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
+ CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
+ CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
+ CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
};
#define EARLY_PGTABLE_SIZE 0x5000
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
index a04a370..b4dea80 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
*/
#include <common.h>
@@ -11,6 +11,22 @@ struct serdes_config {
u8 lanes[SRDS_MAX_LANES];
};
+#ifdef CONFIG_TARGET_LX2162AQDS
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
+ {0x03, {XFI6, XFI5, XFI4, XFI3 } },
+ {0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
+ {0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
+ {0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
+ {0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
+ {0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
+ {0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
+ {0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
+ {}
+};
+#else
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
@@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
{}
};
+#endif
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 820ee97..136f646 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -374,7 +374,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls1028a-rdb.dtb \
fsl-ls1028a-qds.dtb \
fsl-lx2160a-rdb.dtb \
- fsl-lx2160a-qds.dtb
+ fsl-lx2160a-qds.dtb \
+ fsl-lx2162a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
new file mode 100644
index 0000000..2a498af
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2162AQDS device tree source
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2162AQDS Board";
+ compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+
+ aliases {
+ spi0 = &fspi;
+
+ pcie at 3500000 {
+ status = "disabled";
+ };
+
+ pcie at 3800000 {
+ status = "disabled";
+ };
+
+ pcie at 3900000 {
+ status = "disabled";
+ };
+ };
+};
+
+&fspi {
+ bus-num = <0>;
+ status = "okay";
+ fspi-has-second-chip;
+
+ qflash0: mt35xu512g at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
+ fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
+ };
+
+ /*
+ * MCR2[SAMEDEVICEEN] bit is enabled in FlexSPI controller for
+ * LX2160ARDB and LX2160AQDS board. Both these has same type of flash
+ * slave devices connected on both A0 and A1.
+ * No need to provide node info for second flash device.
+ */
+};
+
+&usb1 {
+ status = "disabled";
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ i2c-mux at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc at 51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index c62d414..b678a9f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2015 Freescale Semiconductor
*/
@@ -106,6 +106,9 @@ enum boot_src get_boot_src(void);
#define SVR_LX2160A 0x873600
#define SVR_LX2120A 0x873620
#define SVR_LX2080A 0x873602
+#define SVR_LX2162A 0x873608
+#define SVR_LX2122A 0x873628
+#define SVR_LX2082A 0x87360A
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig
index fc747bb..ce2ef5d 100644
--- a/board/freescale/lx2160a/Kconfig
+++ b/board/freescale/lx2160a/Kconfig
@@ -41,3 +41,19 @@ config SYS_CONFIG_NAME
source "board/freescale/common/Kconfig"
endif
+if TARGET_LX2162AQDS
+
+config SYS_BOARD
+ default "lx2160a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "lx2162aqds"
+
+source "board/freescale/common/Kconfig"
+endif
diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS
index 47ae04c..a4566c4 100644
--- a/board/freescale/lx2160a/MAINTAINERS
+++ b/board/freescale/lx2160a/MAINTAINERS
@@ -1,5 +1,6 @@
LX2160ARDB BOARD
-M: Priyanka Jain <priyanka.jain at nxp.com>
+M: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
+M: Priyanka Jain <priyanka.jain at nxp.com>
S: Maintained
F: board/freescale/lx2160a/
F: include/configs/lx2160a_common.h
@@ -13,6 +14,7 @@ S: Maintained
F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
LX2160AQDS BOARD
+M: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
M: Pankaj Bansal <pankaj.bansal at nxp.com>
S: Maintained
F: board/freescale/lx2160a/eth_lx2160aqds.h
@@ -24,3 +26,13 @@ LX2160AQDS_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal at nxp.com>
S: Maintained
F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+
+LX2162AQDS BOARD
+M: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
+S: Maintained
+F: board/freescale/lx2160a/eth_lx2162aqds.h
+F: include/configs/lx2162aqds.h
+F: configs/lx2162aqds_tfa_defconfig
+F: arch/arm/dts/fsl-lx2162a-qds.dts
+
+
diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile
index d1a621b..c9561bf 100644
--- a/board/freescale/lx2160a/Makefile
+++ b/board/freescale/lx2160a/Makefile
@@ -8,3 +8,4 @@ obj-y += lx2160a.o
obj-y += ddr.o
obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
+obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o
diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c
new file mode 100644
index 0000000..85383fd
--- /dev/null
+++ b/board/freescale/lx2160a/eth_lx2162aqds.c
@@ -0,0 +1,849 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <env.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EMI_NONE 0
+#define EMI1 1 /* Mdio Bus 1 */
+#define EMI2 2 /* Mdio Bus 2 */
+
+#if defined(CONFIG_FSL_MC_ENET)
+enum io_slot {
+ IO_SLOT_NONE = 0,
+ IO_SLOT_1,
+ IO_SLOT_2,
+ IO_SLOT_3,
+ IO_SLOT_4,
+ IO_SLOT_5,
+ IO_SLOT_6,
+ IO_SLOT_7,
+ IO_SLOT_8,
+ EMI1_RGMII1,
+ EMI1_RGMII2,
+ IO_SLOT_MAX
+};
+
+struct lx2162a_qds_mdio {
+ enum io_slot ioslot : 4;
+ u8 realbusnum : 4;
+ struct mii_dev *realbus;
+};
+
+/* structure explaining the phy configuration on 8 lanes of a serdes*/
+struct serdes_phy_config {
+ u8 serdes; /* serdes protocol */
+ struct phy_config {
+ u8 dpmacid;
+ /* -1 terminated array */
+ int phy_address[WRIOP_MAX_PHY_NUM + 1];
+ u8 mdio_bus;
+ enum io_slot ioslot;
+ } phy_config[SRDS_MAX_LANES];
+};
+
+/* Table defining the phy configuration on 8 lanes of a serdes.
+ * Various assumptions have been made while defining this table.
+ * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
+ * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
+ * And also that this card is connected to IO Slot 1 (could have been connected
+ * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
+ * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
+ * used in serdes1 protocol 19 (could have selected MDIO 2)
+ * To override these settings "dpmac" environment variable can be used after
+ * defining "dpmac_override" in hwconfig environment variable.
+ * This table has limited serdes protocol entries. It can be expanded as per
+ * requirement.
+ */
+/*****************************************************************
+ | SERDES_1 PROTOCOL | IO_SLOT | CARD |
+ *****************************************************************
+ | 2 | IO_SLOT_1 | M4-PCIE-SGMII |
+ | 3 | IO_SLOT_1 | M11-USXGMII |
+ | 15 | IO_SLOT_1 | M13-25G |
+ | 17 | IO_SLOT_1 | M13-25G |
+ | 18 | IO_SLOT_1 | M11-USXGMII |
+ | | IO_SLOT_6 | M13-25G |
+ | 20 | IO_SLOT_1 | M7-40G |
+ *****************************************************************
+ */
+static const struct serdes_phy_config serdes1_phy_config[] = {
+ {1, {} },
+ {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_1} } },
+ {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
+ EMI1, IO_SLOT_1} } },
+ {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1} } },
+ {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1} } },
+ {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_6},
+ {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_6} } },
+ {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_1} } }
+};
+
+/*****************************************************************
+ | SERDES_2 PROTOCOL | IO_SLOT | CARD |
+ *****************************************************************
+ | 2 | IO_SLOT_7 | M4-PCIE-SGMII |
+ | | IO_SLOT_8 | M4-PCIE-SGMII |
+ | 3 | IO_SLOT_7 | M4-PCIE-SGMII |
+ | | IO_SLOT_8 | M4-PCIE-SGMII |
+ | 5 | IO_SLOT_7 | M4-PCIE-SGMII |
+ | 10 | IO_SLOT_7 | M4-PCIE-SGMII |
+ | | IO_SLOT_8 | M4-PCIE-SGMII |
+ | 11 | IO_SLOT_7 | M4-PCIE-SGMII |
+ | | IO_SLOT_8 | M4-PCIE-SGMII |
+ | 12 | IO_SLOT_7 | M4-PCIE-SGMII |
+ | | IO_SLOT_8 | M4-PCIE-SGMII |
+ *****************************************************************
+ */
+static const struct serdes_phy_config serdes2_phy_config[] = {
+ {2, {} },
+ {3, {} },
+ {5, {} },
+ {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7} } },
+ {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_8},
+ {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_8},
+ {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_8} } },
+ {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7} } }
+};
+
+static inline
+const struct phy_config *get_phy_config(u8 serdes,
+ const struct serdes_phy_config *table,
+ u8 table_size)
+{
+ int i;
+
+ for (i = 0; i < table_size; i++) {
+ if (table[i].serdes == serdes)
+ return table[i].phy_config;
+ }
+
+ return NULL;
+}
+
+/* BRDCFG4 controls EMI routing for the board.
+ * Bits Function
+ * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
+ * EMI1 00= On-board PHY #1
+ * 01= On-board PHY #2
+ * 10= (reserved)
+ * 11= Slots 1..8 multiplexer and translator.
+ * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
+ * EMI1X 000= Slot #1
+ * 001= Slot #2
+ * 010= Slot #3
+ * 011= Slot #4
+ * 100= Slot #5
+ * 101= Slot #6
+ * 110= Slot #7
+ * 111= Slot #8
+ * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
+ * EMI2 000= Slot #1 (secondary EMI)
+ * 001= Slot #2 (secondary EMI)
+ * 010= Slot #3 (secondary EMI)
+ * 011= Slot #4 (secondary EMI)
+ * 100= Slot #5 (secondary EMI)
+ * 101= Slot #6 (secondary EMI)
+ * 110= Slot #7 (secondary EMI)
+ * 111= Slot #8 (secondary EMI)
+ */
+static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
+{
+ switch (realbusnum) {
+ case EMI1:
+ switch (ioslot) {
+ case EMI1_RGMII1:
+ return 0;
+ case EMI1_RGMII2:
+ return 0x40;
+ default:
+ return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
+ }
+ break;
+ case EMI2:
+ return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
+ default:
+ return -1;
+ }
+}
+
+static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
+{
+ u8 brdcfg4, mux_val, reg;
+
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ reg = brdcfg4;
+ mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+
+ switch (priv->realbusnum) {
+ case EMI1:
+ brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
+ brdcfg4 |= mux_val;
+ break;
+ case EMI2:
+ brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
+ brdcfg4 |= mux_val;
+ break;
+ }
+
+ if (brdcfg4 ^ reg)
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
+ int devad, int regnum)
+{
+ struct lx2162a_qds_mdio *priv = bus->priv;
+
+ lx2162a_qds_mux_mdio(priv);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct lx2162a_qds_mdio *priv = bus->priv;
+
+ lx2162a_qds_mux_mdio(priv);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct lx2162a_qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
+{
+ struct lx2162a_qds_mdio *pmdio;
+ struct mii_dev *bus;
+ /*should be within MDIO_NAME_LEN*/
+ char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
+
+ if (realbusnum == EMI2) {
+ if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
+ printf("invalid ioslot %d\n", ioslot);
+ return NULL;
+ }
+ } else if (realbusnum == EMI1) {
+ if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
+ printf("invalid ioslot %d\n", ioslot);
+ return NULL;
+ }
+ } else {
+ printf("not supported real mdio bus %d\n", realbusnum);
+ return NULL;
+ }
+
+ if (ioslot == EMI1_RGMII1)
+ strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1");
+ else if (ioslot == EMI1_RGMII2)
+ strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2");
+ else
+ sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d",
+ realbusnum, ioslot);
+ bus = miiphy_get_dev_by_name(dummy_mdio_name);
+
+ if (bus)
+ return bus;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate %s bus\n", dummy_mdio_name);
+ return NULL;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate %s private data\n", dummy_mdio_name);
+ free(bus);
+ return NULL;
+ }
+
+ switch (realbusnum) {
+ case EMI1:
+ pmdio->realbus =
+ miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ break;
+ case EMI2:
+ pmdio->realbus =
+ miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ break;
+ }
+
+ if (!pmdio->realbus) {
+ printf("No real mdio bus num %d found\n", realbusnum);
+ free(bus);
+ free(pmdio);
+ return NULL;
+ }
+
+ pmdio->realbusnum = realbusnum;
+ pmdio->ioslot = ioslot;
+ bus->read = lx2162a_qds_mdio_read;
+ bus->write = lx2162a_qds_mdio_write;
+ bus->reset = lx2162a_qds_mdio_reset;
+ strcpy(bus->name, dummy_mdio_name);
+ bus->priv = pmdio;
+
+ if (!mdio_register(bus))
+ return bus;
+
+ printf("No bus with name %s\n", dummy_mdio_name);
+ free(bus);
+ free(pmdio);
+ return NULL;
+}
+
+static inline void do_phy_config(const struct phy_config *phy_config)
+{
+ struct mii_dev *bus;
+ int i, phy_num, phy_address;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (!phy_config[i].dpmacid)
+ continue;
+
+ for (phy_num = 0;
+ phy_num < ARRAY_SIZE(phy_config[i].phy_address);
+ phy_num++) {
+ phy_address = phy_config[i].phy_address[phy_num];
+ if (phy_address == -1)
+ break;
+ wriop_set_phy_address(phy_config[i].dpmacid,
+ phy_num, phy_address);
+ }
+ /*Register the muxing front-ends to the MDIO buses*/
+ bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
+ phy_config[i].ioslot);
+ if (!bus)
+ printf("could not get bus for mdio %d ioslot %d\n",
+ phy_config[i].mdio_bus,
+ phy_config[i].ioslot);
+ else
+ wriop_set_mdio(phy_config[i].dpmacid, bus);
+ }
+}
+
+static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
+ char *env_dpmac)
+{
+ const char *ret;
+ size_t len;
+ u8 realbusnum, ioslot;
+ struct mii_dev *bus;
+ int phy_num;
+ char *phystr = "phy00";
+
+ /*search phy in dpmac arg*/
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ sprintf(phystr, "phy%d", phy_num + 1);
+ ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
+ if (!ret) {
+ /*look for phy instead of phy1*/
+ if (!phy_num)
+ ret = hwconfig_subarg_f(arg_dpmacid, "phy",
+ &len, env_dpmac);
+ if (!ret)
+ continue;
+ }
+
+ if (len != 4 || strncmp(ret, "0x", 2))
+ printf("invalid phy format in %s variable.\n"
+ "specify phy%d for %s in hex format e.g. 0x12\n",
+ env_dpmac, phy_num + 1, arg_dpmacid);
+ else
+ wriop_set_phy_address(dpmac, phy_num,
+ simple_strtoul(ret, NULL, 16));
+ }
+
+ /*search mdio in dpmac arg*/
+ ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
+ if (ret)
+ realbusnum = *ret - '0';
+ else
+ realbusnum = EMI_NONE;
+
+ if (realbusnum) {
+ /*search io in dpmac arg*/
+ ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
+ if (ret)
+ ioslot = *ret - '0';
+ else
+ ioslot = IO_SLOT_NONE;
+ /*Register the muxing front-ends to the MDIO buses*/
+ bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
+ if (!bus)
+ printf("could not get bus for mdio %d ioslot %d\n",
+ realbusnum, ioslot);
+ else
+ wriop_set_mdio(dpmac, bus);
+ }
+}
+
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ struct memac_mdio_info mdio_info;
+ struct memac_mdio_controller *regs;
+ int i;
+ const char *ret;
+ char *env_dpmac;
+ char dpmacid[] = "dpmac00", srds[] = "00_00_00";
+ size_t len;
+ struct mii_dev *bus;
+ const struct phy_config *phy_config;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1, srds_s2;
+
+ srds_s1 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ srds_s2 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ sprintf(srds, "%d_%d", srds_s1, srds_s2);
+
+ regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = regs;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /*Register the EMI 1*/
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ mdio_info.regs = regs;
+ mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+ /*Register the EMI 2*/
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ /* "dpmac" environment variable can be used after
+ * defining "dpmac_override" in hwconfig environment variable.
+ */
+ if (hwconfig("dpmac_override")) {
+ env_dpmac = env_get("dpmac");
+ if (env_dpmac) {
+ ret = hwconfig_arg_f("srds", &len, env_dpmac);
+ if (ret) {
+ if (strncmp(ret, srds, strlen(srds))) {
+ printf("SERDES configuration changed.\n"
+ "previous: %.*s, current: %s.\n"
+ "update dpmac variable.\n",
+ (int)len, ret, srds);
+ }
+ } else {
+ printf("SERDES configuration not found.\n"
+ "Please add srds:%s in dpmac variable\n",
+ srds);
+ }
+
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+ /* Look for dpmac1 to dpmac24(current max) arg
+ * in dpmac environment variable
+ */
+ sprintf(dpmacid, "dpmac%d", i);
+ ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
+ if (ret)
+ do_dpmac_config(i, dpmacid, env_dpmac);
+ }
+ } else {
+ printf("Warning: environment dpmac not found.\n"
+ "DPAA network interfaces may not work\n");
+ }
+ } else {
+ /*Look for phy config for serdes1 in phy config table*/
+ phy_config = get_phy_config(srds_s1, serdes1_phy_config,
+ ARRAY_SIZE(serdes1_phy_config));
+ if (!phy_config) {
+ printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
+ __func__, srds_s1);
+ } else {
+ do_phy_config(phy_config);
+ }
+ phy_config = get_phy_config(srds_s2, serdes2_phy_config,
+ ARRAY_SIZE(serdes2_phy_config));
+ if (!phy_config) {
+ printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
+ __func__, srds_s2);
+ } else {
+ do_phy_config(phy_config);
+ }
+ }
+
+ if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
+ bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
+ if (!bus)
+ printf("could not get bus for RGMII1\n");
+ else
+ wriop_set_mdio(WRIOP1_DPMAC17, bus);
+ }
+
+ if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
+ wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
+ bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
+ if (!bus)
+ printf("could not get bus for RGMII2\n");
+ else
+ wriop_set_mdio(WRIOP1_DPMAC18, bus);
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+#ifdef CONFIG_PHY_AQUANTIA
+ /*
+ * Export functions to be used by AQ firmware
+ * upload application
+ */
+ gd->jt->strcpy = strcpy;
+ gd->jt->mdelay = mdelay;
+ gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+ gd->jt->phy_find_by_mask = phy_find_by_mask;
+ gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+ gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_FSL_MC_ENET)
+int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
+{
+ int offset;
+ int ret;
+ char dpmac_str[] = "dpmacs at 00";
+ const char *phy_string;
+
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
+
+ if (offset < 0) {
+ printf("dpmacs node not found in device tree\n");
+ return offset;
+ }
+
+ sprintf(dpmac_str, "dpmac@%x", dpmac_id);
+ debug("dpmac_str = %s\n", dpmac_str);
+
+ offset = fdt_subnode_offset(fdt, offset, dpmac_str);
+ if (offset < 0) {
+ printf("%s node not found in device tree\n", dpmac_str);
+ return offset;
+ }
+
+ ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
+ if (ret)
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+ phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
+ ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
+ phy_string);
+ if (ret)
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+ return ret;
+}
+
+int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
+{
+ char mdio_ioslot_str[] = "mdio at 00";
+ struct lx2162a_qds_mdio *priv;
+ u64 reg;
+ u32 phandle;
+ int offset, mux_val;
+
+ /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
+ if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
+ strlen("LX2162A_QDS_MDIO")))
+ return -1;
+
+ /*Get the real MDIO bus num and ioslot info from bus's priv data*/
+ priv = mii_dev->priv;
+
+ debug("real_bus_num = %d, ioslot = %d\n",
+ priv->realbusnum, priv->ioslot);
+
+ if (priv->realbusnum == EMI1)
+ reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ else
+ reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+
+ offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
+ if (offset < 0) {
+ printf("mdio@%llx node not found in device tree\n", reg);
+ return offset;
+ }
+
+ phandle = fdt_get_phandle(fdt, offset);
+ phandle = cpu_to_fdt32(phandle);
+ offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
+ &phandle, 4);
+ if (offset < 0) {
+ printf("mdio-mux-%d node not found in device tree\n",
+ priv->realbusnum == EMI1 ? 1 : 2);
+ return offset;
+ }
+
+ mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+ if (priv->realbusnum == EMI1)
+ mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
+ else
+ mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
+ sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
+
+ offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
+ if (offset < 0) {
+ printf("%s node not found in device tree\n", mdio_ioslot_str);
+ return offset;
+ }
+
+ return offset;
+}
+
+int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
+ struct phy_device *phy_dev, int phandle)
+{
+ char phy_node_name[] = "ethernet-phy at 00";
+ char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
+ int ret;
+
+ sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
+ debug("phy_node_name = %s\n", phy_node_name);
+
+ *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
+ if (*subnodeoffset <= 0) {
+ printf("Could not add subnode %s inside node %s err = %s\n",
+ phy_node_name, fdt_get_name(fdt, offset, NULL),
+ fdt_strerror(*subnodeoffset));
+ return *subnodeoffset;
+ }
+
+ sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
+ phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
+ debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
+
+ ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
+ phy_id_compatible_str);
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+
+ if (phy_dev->is_c45) {
+ ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+ "ethernet-phy-ieee802.3-c45");
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+ } else {
+ ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+ "ethernet-phy-ieee802.3-c22");
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+ }
+
+ ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+
+ ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+
+out:
+ if (ret)
+ fdt_del_node(fdt, *subnodeoffset);
+
+ return ret;
+}
+
+#define is_rgmii(dpmac_id) \
+ wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID
+
+int fdt_fixup_board_phy(void *fdt)
+{
+ int fpga_offset, offset, subnodeoffset;
+ struct mii_dev *mii_dev;
+ struct list_head *mii_devs, *entry;
+ int ret, dpmac_id, phandle, i;
+ struct phy_device *phy_dev;
+ char ethname[ETH_NAME_LEN];
+ phy_interface_t phy_iface;
+
+ ret = 0;
+ /* we know FPGA is connected to i2c0, therefore search path directly,
+ * instead of compatible property, as it saves time
+ */
+ fpga_offset = fdt_path_offset(fdt, "/soc/i2c at 2000000/fpga");
+
+ if (fpga_offset < 0)
+ fpga_offset = fdt_path_offset(fdt, "/i2c at 2000000/fpga");
+
+ if (fpga_offset < 0) {
+ printf("i2c at 2000000/fpga node not found in device tree\n");
+ return fpga_offset;
+ }
+
+ phandle = fdt_alloc_phandle(fdt);
+ mii_devs = mdio_get_list_head();
+
+ list_for_each(entry, mii_devs) {
+ mii_dev = list_entry(entry, struct mii_dev, link);
+ debug("mii_dev name : %s\n", mii_dev->name);
+ offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
+ if (offset < 0)
+ continue;
+
+ // Look for phy devices attached to MDIO bus muxing front end
+ // and create their entries with compatible being the device id
+ for (i = 0; i < PHY_MAX_ADDR; i++) {
+ phy_dev = mii_dev->phymap[i];
+ if (!phy_dev)
+ continue;
+
+ // TODO: use sscanf instead of loop
+ dpmac_id = WRIOP1_DPMAC1;
+ while (dpmac_id < NUM_WRIOP_PORTS) {
+ phy_iface = wriop_get_enet_if(dpmac_id);
+ snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
+ dpmac_id,
+ phy_string_for_interface(phy_iface));
+ if (strcmp(ethname, phy_dev->dev->name) == 0)
+ break;
+ dpmac_id++;
+ }
+ if (dpmac_id == NUM_WRIOP_PORTS)
+ continue;
+
+ if ((dpmac_id == 17 || dpmac_id == 18) &&
+ is_rgmii(dpmac_id))
+ continue;
+
+ ret = fdt_create_phy_node(fdt, offset, i,
+ &subnodeoffset,
+ phy_dev, phandle);
+ if (ret)
+ break;
+
+ ret = fdt_fixup_dpmac_phy_handle(fdt,
+ dpmac_id, phandle);
+ if (ret) {
+ fdt_del_node(fdt, subnodeoffset);
+ break;
+ }
+ /* calculate offset again as new node addition may have
+ * changed offset;
+ */
+ offset = fdt_get_ioslot_offset(fdt, mii_dev,
+ fpga_offset);
+ phandle++;
+ }
+
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+#endif // CONFIG_FSL_MC_ENET
+
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 775acbd..2a54d5f 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -37,7 +37,7 @@
#endif
#define GIC_LPI_SIZE 0x200000
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
@@ -47,7 +47,7 @@
#define SDHC1_BASE_PMUX_DSPI 2
#define SDHC2_BASE_PMUX_DSPI 2
#define IIC5_PMUX_SPI3 3
-#endif /* CONFIG_TARGET_LX2160AQDS */
+#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
DECLARE_GLOBAL_DATA_PTR;
@@ -212,7 +212,7 @@ int board_fix_fdt(void *fdt)
}
#endif
-#if defined(CONFIG_TARGET_LX2160AQDS)
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
void esdhc_dspi_status_fixup(void *blob)
{
const char esdhc0_path[] = "/soc/esdhc at 2140000";
@@ -280,7 +280,7 @@ void esdhc_dspi_status_fixup(void *blob)
int esdhc_status_fixup(void *blob, const char *compat)
{
-#if defined(CONFIG_TARGET_LX2160AQDS)
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
/* Enable esdhc and dspi DT nodes based on RCW fields */
esdhc_dspi_status_fixup(blob);
#else
@@ -318,7 +318,7 @@ int checkboard(void)
enum boot_src src = get_boot_src();
char buf[64];
u8 sw;
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
int clock;
static const char *const freq[] = {"100", "125", "156.25",
"161.13", "322.26", "", "", "",
@@ -327,7 +327,7 @@ int checkboard(void)
#endif
cpu_name(buf);
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
printf("Board: %s-QDS, ", buf);
#else
printf("Board: %s-RDB, ", buf);
@@ -360,7 +360,13 @@ int checkboard(void)
break;
}
}
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160ARDB)
+ printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+
+ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
+ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+#else
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
@@ -371,31 +377,27 @@ int checkboard(void)
sw = QIXIS_READ(brdcfg[2]);
clock = sw >> 4;
printf("Clock1 = %sMHz ", freq[clock]);
+#if defined(CONFIG_TARGET_LX2160AQDS)
clock = sw & 0x0f;
printf("Clock2 = %sMHz", freq[clock]);
-
+#endif
sw = QIXIS_READ(brdcfg[3]);
puts("\nSERDES2 Reference : ");
clock = sw >> 4;
printf("Clock1 = %sMHz ", freq[clock]);
clock = sw & 0x0f;
- printf("Clock2 = %sMHz", freq[clock]);
-
+ printf("Clock2 = %sMHz\n", freq[clock]);
+#if defined(CONFIG_TARGET_LX2160AQDS)
sw = QIXIS_READ(brdcfg[12]);
- puts("\nSERDES3 Reference : ");
+ puts("SERDES3 Reference : ");
clock = sw >> 4;
printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
-#else
- printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
- puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
- puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
- puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+#endif
#endif
return 0;
}
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
/*
* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
*/
@@ -552,7 +554,7 @@ int config_board_mux(void)
unsigned long get_board_sys_clk(void)
{
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x03) {
@@ -571,7 +573,7 @@ unsigned long get_board_sys_clk(void)
unsigned long get_board_ddr_clk(void)
{
-#ifdef CONFIG_TARGET_LX2160AQDS
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..b2ae694
--- /dev/null
+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LX2162AQDS=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_NXP_ESBC=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SBSA=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_DM_RTC=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_DATE=y
+CONFIG_RTC_PCF2127=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
new file mode 100644
index 0000000..47c98ec
--- /dev/null
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LX2162AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_DM_GPIO=y
+CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x20500000
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_PHY_INPHI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_DM_RTC=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_DATE=y
+CONFIG_RTC_PCF2127=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig
new file mode 100644
index 0000000..49b14d1
--- /dev/null
+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LX2162AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x500000
+CONFIG_FSPI_AHB_EN_4BYTE=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_RSA=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x20500000
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_DSPI=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_PHY_INPHI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SBSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_GIC_V3_ITS=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_DM_RTC=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_DATE=y
+CONFIG_RTC_PCF2127=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_CMD_OPTEE_RPMB=y
+CONFIG_OPTEE_TA_AVB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index d8c9e71..3aa8214 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -589,7 +589,9 @@ static int ls_pcie_probe(struct udevice *dev)
pcie->ctrl = pcie->lut + 0x40000;
}
- if (svr == SVR_LX2160A)
+ if (svr == SVR_LX2160A || svr == SVR_LX2162A ||
+ svr == SVR_LX2120A || svr == SVR_LX2080A ||
+ svr == SVR_LX2122A || svr == SVR_LX2082A)
pcie->pf1_offset = LX2160_PCIE_PF1_OFFSET;
else
pcie->pf1_offset = LS_PCIE_PF1_OFFSET;
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
index b010a63..cbbf4bce 100644
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -94,7 +94,10 @@ int pcie_board_fix_fdt(void *fdt)
svr = SVR_SOC_VER(get_svr());
- if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0))
+ if ((svr == SVR_LX2160A || svr == SVR_LX2162A ||
+ svr == SVR_LX2120A || svr == SVR_LX2080A ||
+ svr == SVR_LX2122A || svr == SVR_LX2082A) &&
+ IS_SVR_REV(get_svr(), 2, 0))
return lx2_board_fix_fdt(fdt);
return 0;
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 1bfca02..793cc49 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -162,8 +162,10 @@
/* USB */
#ifdef CONFIG_USB
#define CONFIG_HAS_FSL_XHCI_USB
+#ifndef CONFIG_TARGET_LX2162AQDS
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
+#endif
/* FlexSPI */
#ifdef CONFIG_NXP_FSPI
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 876ad66..203d8e5 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -137,7 +137,7 @@ u8 qixis_esdhc_detect_quirk(void);
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$BOARD\0" \
"sd_bootcmd=echo Trying load from sd card..;" \
- "mmcinfo; mmc read $load_addr " \
+ "mmc dev 0; mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 0d6dd51..3047414 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -107,7 +107,7 @@
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$BOARD\0" \
"sd_bootcmd=echo Trying load from sd card..;" \
- "mmcinfo; mmc read $load_addr " \
+ "mmc dev 0; mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
new file mode 100644
index 0000000..d364660
--- /dev/null
+++ b/include/configs/lx2162aqds.h
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __LX2162_QDS_H
+#define __LX2162_QDS_H
+
+#include "lx2160a_common.h"
+
+/* USB */
+#undef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+/*
+ * Need to override existing (lx2160a) with lx2162aqds so set_board_info will
+ * use proper prefix when creating full board_name (SYS_BOARD + type)
+ */
+#undef CONFIG_SYS_BOARD
+#define CONFIG_SYS_BOARD "lx2162aqds"
+
+#undef CONFIG_SYS_NXP_SRDS_3
+
+/* Qixis */
+#define QIXIS_XMAP_MASK 0x07
+#define QIXIS_XMAP_SHIFT 5
+#define QIXIS_RST_CTL_RESET_EN 0x30
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x20
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
+#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
+#define NON_EXTENDED_DUTCFG
+#define QIXIS_SDID_MASK 0x07
+#define QIXIS_ESDHC_NO_ADAPTER 0x7
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_100 0x0
+#define QIXIS_SYSCLK_125 0x1
+#define QIXIS_SYSCLK_133 0x2
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_100 0x0
+#define QIXIS_DDRCLK_125 0x1
+#define QIXIS_DDRCLK_133 0x2
+
+#define BRDCFG4_EMI1SEL_MASK 0xF8
+#define BRDCFG4_EMI1SEL_SHIFT 3
+#define BRDCFG4_EMI2SEL_MASK 0x07
+#define BRDCFG4_EMI2SEL_SHIFT 0
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN 775
+#define VDD_MV_MAX 925
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+#define PWM_CHANNEL0 0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 0
+#define I2C_MUX_CH_RTC 0xB
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#ifndef __ASSEMBLY__
+u8 qixis_esdhc_detect_quirk(void);
+#endif
+#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
+#endif
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC17 at rgmii-id"
+
+#define AQ_PHY_ADDR1 0x00
+#define AQ_PHY_ADDR2 0x01
+#define AQ_PHY_ADDR3 0x02
+#define AQ_PHY_ADDR4 0x03
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1 0x0
+
+#define INPHI_PHY_ADDR1 0x0
+#define INPHI_PHY_ADDR2 0x1
+#ifdef CONFIG_SD_BOOT
+#define IN112525_FW_ADDR 0x980000
+#else
+#define IN112525_FW_ADDR 0x20980000
+#endif
+#define IN112525_FW_LENGTH 0x40000
+
+#define RGMII_PHY_ADDR1 0x01
+#define RGMII_PHY_ADDR2 0x02
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#endif
+
+/* DSPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "boot_scripts=lx2162aqds_boot.scr\0" \
+ "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \
+ "BOARD=lx2162aqds\0" \
+ "xspi_bootcmd=echo Trying load from flexspi..;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmc dev 0; mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0" \
+ "emmc_bootcmd=echo Trying load from emmc card..;" \
+ "mmc dev 1; mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2162_QDS_H */
--
2.7.4
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