[PATCH 18/31] misc: am33xx: add control module driver

Dario Binacchi dariobin at libero.it
Tue Aug 25 11:21:11 CEST 2020


The implementation of this driver was needed to bind the device tree
sub-nodes of the 'clocks' node. In fact, the lack of the compatible
property in the 'clocks' node does not allow the generic 'syscon' or
'simple-bus' drivers linked to the 'scm_conf at 0' node to bind the
'clocks' node and in turn its sub-nodes.
The 'scm at 210000' node is therefore the node closest to the 'clocks' node
whose driver can bind all the 'clocks' sub-nodes.

scm: scm at 210000 {
	compatible = "ti,am3-scm", "simple-bus";
	...

	scm_conf: scm_conf at 0 {
		compatible = "syscon", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x800>;

		scm_clocks: clocks {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};

Signed-off-by: Dario Binacchi <dariobin at libero.it>
---

 doc/device-tree-bindings/arm/omap,ctrl.txt    |  82 ++++++
 .../pinctrl/pinctrl-single.txt                | 255 ++++++++++++++++++
 drivers/misc/Kconfig                          |   7 +
 drivers/misc/Makefile                         |   1 +
 drivers/misc/ti-am3-scm.c                     |  90 +++++++
 5 files changed, 435 insertions(+)
 create mode 100644 doc/device-tree-bindings/arm/omap,ctrl.txt
 create mode 100644 doc/device-tree-bindings/pinctrl/pinctrl-single.txt
 create mode 100644 drivers/misc/ti-am3-scm.c

diff --git a/doc/device-tree-bindings/arm/omap,ctrl.txt b/doc/device-tree-bindings/arm/omap,ctrl.txt
new file mode 100644
index 0000000000..8efd321cfa
--- /dev/null
+++ b/doc/device-tree-bindings/arm/omap,ctrl.txt
@@ -0,0 +1,82 @@
+OMAP Control Module bindings
+
+Control Module contains miscellaneous features under it based on SoC type.
+Pincontrol is one common feature, and it has a specialized support
+described in [1]. Typically some clock nodes are also under control module.
+Syscon is used to share register level access to drivers external to
+control module driver itself.
+
+See [2] for documentation about clock/clockdomain nodes.
+
+[1] doc/device-tree-bindings/pinctrl/pinctrl-single.txt
+[2] doc/device-tree-bindings/clock/ti,*.txt
+
+Required properties:
+- compatible:	Must be one of:
+		"ti,am3-scm"
+		"ti,am4-scm"
+		"ti,dm814-scrm"
+		"ti,dm816-scrm"
+		"ti,omap2-scm"
+		"ti,omap3-scm"
+		"ti,omap4-scm-core"
+		"ti,omap4-scm-padconf-core"
+		"ti,omap4-scm-wkup"
+		"ti,omap4-scm-padconf-wkup"
+		"ti,omap5-scm-core"
+		"ti,omap5-scm-padconf-core"
+		"ti,omap5-scm-wkup-pad-conf"
+		"ti,dra7-scm-core"
+- reg:		Contains Control Module register address range
+		(base address and length)
+
+Optional properties:
+- clocks:	clocks for this module
+- clockdomains:	clockdomains for this module
+
+Examples:
+
+scm: scm at 2000 {
+	compatible = "ti,omap3-scm", "simple-bus";
+	reg = <0x2000 0x2000>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0x2000 0x2000>;
+
+	omap3_pmx_core: pinmux at 30 {
+		compatible = "ti,omap3-padconf",
+			     "pinctrl-single";
+		reg = <0x30 0x230>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		pinctrl-single,register-width = <16>;
+		pinctrl-single,function-mask = <0xff1f>;
+	};
+
+	scm_conf: scm_conf at 270 {
+		compatible = "syscon";
+		reg = <0x270 0x330>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		scm_clocks: clocks {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	scm_clockdomains: clockdomains {
+	};
+}
+
+&scm_clocks {
+	mcbsp5_mux_fck: mcbsp5_mux_fck {
+		#clock-cells = <0>;
+		compatible = "ti,composite-mux-clock";
+		clocks = <&core_96m_fck>, <&mcbsp_clks>;
+		ti,bit-shift = <4>;
+		reg = <0x02d8>;
+	};
+};
diff --git a/doc/device-tree-bindings/pinctrl/pinctrl-single.txt b/doc/device-tree-bindings/pinctrl/pinctrl-single.txt
new file mode 100644
index 0000000000..e705acd361
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/pinctrl-single.txt
@@ -0,0 +1,255 @@
+One-register-per-pin type device tree based pinctrl driver
+
+Required properties:
+- compatible : "pinctrl-single" or "pinconf-single".
+  "pinctrl-single" means that pinconf isn't supported.
+  "pinconf-single" means that generic pinconf is supported.
+
+- reg : offset and length of the register set for the mux registers
+
+- #pinctrl-cells : number of cells in addition to the index, set to 1
+  for pinctrl-single,pins and 2 for pinctrl-single,bits
+
+- pinctrl-single,register-width : pinmux register access width in bits
+
+- pinctrl-single,function-mask : mask of allowed pinmux function bits
+  in the pinmux register
+
+Optional properties:
+- pinctrl-single,function-off : function off mode for disabled state if
+  available and same for all registers; if not specified, disabling of
+  pin functions is ignored
+
+- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
+  more than one pin, for which "pinctrl-single,function-mask" property specifies
+ position mask of pin.
+
+- pinctrl-single,drive-strength : array of value that are used to configure
+  drive strength in the pinmux register. They're value of drive strength
+  current and drive strength mask.
+
+		/* drive strength current, mask */
+		pinctrl-single,power-source = <0x30 0xf0>;
+
+- pinctrl-single,bias-pullup : array of value that are used to configure the
+  input bias pullup in the pinmux register.
+
+		/* input, enabled pullup bits, disabled pullup bits, mask */
+		pinctrl-single,bias-pullup = <0 1 0 1>;
+
+- pinctrl-single,bias-pulldown : array of value that are used to configure the
+  input bias pulldown in the pinmux register.
+
+		/* input, enabled pulldown bits, disabled pulldown bits, mask */
+		pinctrl-single,bias-pulldown = <2 2 0 2>;
+
+  * Two bits to control input bias pullup and pulldown: User should use
+    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
+    pullup, and the other one bit means pulldown.
+  * Three bits to control input bias enable, pullup and pulldown. User should
+    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
+    enable bit should be included in pullup or pulldown bits.
+  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
+    pinctrl-single,bias-disable. Because pinctrl single driver could implement
+    it by calling pulldown, pullup disabled.
+
+- pinctrl-single,input-schmitt : array of value that are used to configure
+  input schmitt in the pinmux register. In some silicons, there're two input
+  schmitt value (rising-edge & falling-edge) in the pinmux register.
+
+		/* input schmitt value, mask */
+		pinctrl-single,input-schmitt = <0x30 0x70>;
+
+- pinctrl-single,input-schmitt-enable : array of value that are used to
+  configure input schmitt enable or disable in the pinmux register.
+
+		/* input, enable bits, disable bits, mask */
+		pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
+
+- pinctrl-single,low-power-mode : array of value that are used to configure
+  low power mode of this pin. For some silicons, the low power mode will
+  control the output of the pin when the pad including the pin enter low
+  power mode.
+		/* low power mode value, mask */
+		pinctrl-single,low-power-mode = <0x288 0x388>;
+
+- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
+  range. They're value of subnode phandle, pin base in pinctrl device, pin
+  number in this range, GPIO function value of this GPIO range.
+  The number of parameters is depend on #pinctrl-single,gpio-range-cells
+  property.
+
+		/* pin base, nr pins & gpio function */
+		pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
+
+- interrupt-controller : standard interrupt controller binding if using
+  interrupts for wake-up events for example. In this case pinctrl-single
+  is set up as a chained interrupt controller and the wake-up interrupts
+  can be requested by the drivers using request_irq().
+
+- #interrupt-cells : standard interrupt binding if using interrupts
+
+This driver assumes that there is only one register for each pin (unless the
+pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
+specified in the pinctrl-bindings.txt document in this directory.
+
+The pin configuration nodes for pinctrl-single are specified as pinctrl
+register offset and value pairs using pinctrl-single,pins. Only the bits
+specified in pinctrl-single,function-mask are updated. For example, setting
+a pin for a device could be done with:
+
+	pinctrl-single,pins = <0xdc 0x118>;
+
+Where 0xdc is the offset from the pinctrl register base address for the
+device pinctrl register, and 0x118 contains the desired value of the
+pinctrl register. See the device example and static board pins example
+below for more information.
+
+In case when one register changes more than one pin's mux the
+pinctrl-single,bits need to be used which takes three parameters:
+
+	pinctrl-single,bits = <0xdc 0x18 0xff>;
+
+Where 0xdc is the offset from the pinctrl register base address for the
+device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
+be used when applying this change to the register.
+
+
+Optional sub-node: In case some pins could be configured as GPIO in the pinmux
+register, those pins could be defined as a GPIO range. This sub-node is required
+by pinctrl-single,gpio-range property.
+
+Required properties in sub-node:
+- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
+  pinctrl-single,gpio-range property.
+
+	range: gpio-range {
+		#pinctrl-single,gpio-range-cells = <3>;
+	};
+
+
+Example:
+
+/* SoC common file */
+
+/* first controller instance for pins in core domain */
+pmx_core: pinmux at 4a100040 {
+	compatible = "pinctrl-single";
+	reg = <0x4a100040 0x0196>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	#interrupt-cells = <1>;
+	interrupt-controller;
+	pinctrl-single,register-width = <16>;
+	pinctrl-single,function-mask = <0xffff>;
+};
+
+/* second controller instance for pins in wkup domain */
+pmx_wkup: pinmux at 4a31e040 {
+	compatible = "pinctrl-single";
+	reg = <0x4a31e040 0x0038>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	#interrupt-cells = <1>;
+	interrupt-controller;
+	pinctrl-single,register-width = <16>;
+	pinctrl-single,function-mask = <0xffff>;
+};
+
+control_devconf0: pinmux at 48002274 {
+	compatible = "pinctrl-single";
+	reg = <0x48002274 4>;	/* Single register */
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-single,bit-per-mux;
+	pinctrl-single,register-width = <32>;
+	pinctrl-single,function-mask = <0x5F>;
+};
+
+/* third controller instance for pins in gpio domain */
+pmx_gpio: pinmux at d401e000 {
+	compatible = "pinconf-single";
+	reg = <0xd401e000 0x0330>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	pinctrl-single,register-width = <32>;
+	pinctrl-single,function-mask = <7>;
+
+	/* sparse GPIO range could be supported */
+	pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
+				&range 12 1 0 &range 13 29 1
+				&range 43 1 0 &range 44 49 1
+				&range 94 1 1 &range 96 2 1>;
+
+	range: gpio-range {
+		#pinctrl-single,gpio-range-cells = <3>;
+	};
+};
+
+
+/* board specific .dts file */
+
+&pmx_core {
+
+	/*
+	 * map all board specific static pins enabled by the pinctrl driver
+	 * itself during the boot (or just set them up in the bootloader)
+	 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&board_pins>;
+
+	board_pins: pinmux_board_pins {
+		pinctrl-single,pins = <
+			0x6c 0xf
+			0x6e 0xf
+			0x70 0xf
+			0x72 0xf
+		>;
+	};
+
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			0x208 0		/* UART0_RXD (IOCFG138) */
+			0x20c 0		/* UART0_TXD (IOCFG139) */
+		>;
+		pinctrl-single,bias-pulldown = <0 2 2>;
+		pinctrl-single,bias-pullup = <0 1 1>;
+	};
+
+	/* map uart2 pins */
+	uart2_pins: pinmux_uart2_pins {
+		pinctrl-single,pins = <
+			0xd8 0x118
+			0xda 0
+			0xdc 0x118
+			0xde 0
+		>;
+	};
+};
+
+&control_devconf0 {
+	mcbsp1_pins: pinmux_mcbsp1_pins {
+		pinctrl-single,bits = <
+			0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
+		>;
+	};
+
+	mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
+		pinctrl-single,bits = <
+			0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
+		>;
+	};
+
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_pins>;
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index b67e906a76..9e8b676637 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -500,4 +500,11 @@ config ESM_PMIC
 	  Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
 	  typically to reboot the board in error condition.
 
+config TI_AM3_SCM
+	bool "AM33XX specific control module support (SCM)"
+	depends on ARCH_OMAP2PLUS
+	help
+	 The control module includes status and control logic not addressed
+	 within the peripherals or the rest of the device infrastructure.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 947bd3a647..056fb3b522 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
 obj-$(CONFIG_K3_AVS0) += k3_avs.o
 obj-$(CONFIG_ESM_K3) += k3_esm.o
 obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
+obj-$(CONFIG_TI_AM3_SCM) += ti-am3-scm.o
diff --git a/drivers/misc/ti-am3-scm.c b/drivers/misc/ti-am3-scm.c
new file mode 100644
index 0000000000..e5f4f09261
--- /dev/null
+++ b/drivers/misc/ti-am3-scm.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AM335x specific control module (scm)
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin at libero.it>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <linux/err.h>
+
+static int ti_am3_scm_bind(struct udevice *dev)
+{
+	int err;
+	struct udevice *conf_dev;
+	ofnode clocks_node, conf_node;
+
+	err = dm_scan_fdt_dev(dev);
+	if (err) {
+		dev_err(dev, "%s: dm_scan_fdt, err=%d\n", __func__, err);
+		return err;
+	}
+
+	conf_node = dev_read_subnode(dev, "scm_conf at 0");
+	if (!ofnode_valid(conf_node)) {
+		dev_err(dev, "%s: failed to get conf sub-node\n", __func__);
+		return -ENODEV;
+	}
+
+	if (uclass_get_device_by_ofnode(UCLASS_SYSCON, conf_node, &conf_dev)) {
+		if (uclass_get_device_by_ofnode(UCLASS_SIMPLE_BUS, conf_node,
+						&conf_dev)) {
+			dev_err(dev, "%s: failed to get conf device\n",
+				__func__);
+			return -ENODEV;
+		}
+	}
+
+	clocks_node = dev_read_subnode(conf_dev, "clocks");
+	if (!ofnode_valid(clocks_node)) {
+		dev_err(dev, "%s: failed to get clocks sub-node\n", __func__);
+		return -ENODEV;
+	}
+
+	err = device_bind_driver_to_node(conf_dev, "ti_am3_scm_clocks",
+					 "scm_clocks", clocks_node, NULL);
+	if (err) {
+		dev_err(dev, "%s: failed to bind scm_clocks\n", __func__);
+		return err;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id ti_am3_scm_ids[] = {
+	{.compatible = "ti,am3-scm"},
+	{}
+};
+
+U_BOOT_DRIVER(ti_am3_scm) = {
+	.name = "ti_am3_scm",
+	.id = UCLASS_SIMPLE_BUS,
+	.of_match = ti_am3_scm_ids,
+	.bind = ti_am3_scm_bind,
+};
+
+static int ti_am3_scm_clocks_bind(struct udevice *dev)
+{
+	ofnode node;
+	int err;
+
+	dev_dbg(dev, "%s: dev=%p\n", __func__, dev);
+	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+		err = lists_bind_fdt(dev, node, NULL, false);
+		if (err) {
+			dev_err(dev, "%s: lists_bind_fdt, err=%d\n",
+				__func__, err);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(ti_am3_scm_clocks) = {
+	.name = "ti_am3_scm_clocks",
+	.id = UCLASS_SIMPLE_BUS,
+	.bind = ti_am3_scm_clocks_bind,
+};
-- 
2.17.1



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