[PATCH v3 1/1] Makefile: socfpga: Generate sfp file with 4 SPL images

[Tan, Ley Foon]

> -----Original Message-----
> From: Ang, Chee Hong <chee.hong.ang at intel.com>
> Sent: Tuesday, August 11, 2020 9:53 PM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex at denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Tom Rini <trini at konsulko.com>; See,
> Chin Liang <chin.liang.see at intel.com>; Tan, Ley Foon
> <ley.foon.tan at intel.com>; Ang, Chee Hong <chee.hong.ang at intel.com>;
> Chee, Tien Fong <tien.fong.chee at intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim at intel.com>
> Subject: [PATCH v3 1/1] Makefile: socfpga: Generate sfp file with 4 SPL
> images
> 
> Generate 'u-boot-splx4.sfp' which consist of 4 SPL images required for
> booting up Cyclone5/Arria10.
> 
> By default, this 'u-boot-splx4.sfp' is generated without extra padding after
> each SPL image.
> 
> For Cyclone5, 'u-boot-splx4.sfp' contains:
> 4 x SPL(64KB) = 256KB
> 
> For Arria10, 'u-boot-splx4.sfp' contains:
> 4 x SPL(256KB) = 1024KB
> 
> For Cyclone5 using NAND flash image layout for 128 KB memory blocks, user
> can 'make' the following target to generate 4 SPL images with
> padding:
> 
> make u-boot-spl-padx4.sfp
> 
> 'u-boot-spl-padx4.sfp' contains four 128KB SPL images (each 64KB SPL is
> followed by 64KB of zero-padding).
> 4 x (SPL(64KB) + zero-padding(64KB)) = 512KB
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang at intel.com>
> ---
> v3 changes:
> - add 'u-boot-splx4.sfp' make target (4 x SPL image without paddings)
> - add 'u-boot-spl-padx4.sfp' make target (4 x SPL image with 64KB paddings)
> - Update commit message (refer to commit message for details explanation)
> 
>  Makefile | 27 ++++++++++++++++++---------
>  1 file changed, 18 insertions(+), 9 deletions(-)


Reviewed-by: Ley Foon Tan <ley.foon.tan at intel.com>