[PATCH v2 6/9] ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)
sr at denx.de
Thu Aug 27 08:47:49 CEST 2020
On 21.08.20 13:25, Stefan Roese wrote:
> Hi Daniel,
> On 19.08.20 16:47, Daniel Schwierzeck wrote:
>> Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese:
>>> From: Aaron Williams <awilliams at marvell.com>
>>> This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
>>> repository. It currently supports DDR4 on Octeon 3. It can be later
>>> extended to support also DDR3 and Octeon 2 platforms.
>>> Part 2 includes the very complex Octeon 3 DDR4 configuration
>>> Signed-off-by: Aaron Williams <awilliams at marvell.com>
>>> Signed-off-by: Stefan Roese <sr at denx.de>
>>> (no changes since v1)
>>> drivers/ram/octeon/octeon3_lmc.c | 11484 +++++++++++++++++++++++++++++
>>> 1 file changed, 11484 insertions(+)
>>> create mode 100644 drivers/ram/octeon/octeon3_lmc.c
>> some general notes:
>> - there are a lot of C++ style comments
> Again, please see my comments on this from the earlier mail.
>> - there are some internal configuration variables and according code
>> which is not built. Can't you remove that to cut down the code size? Or
>> convert to Kconfig symbols if the code is needed.
> I'm checking these options right now and will get back to you on this
Sorry for the delay. It took some time to get this sorted out.
I'll remove all local defines / options that result in dead code, e.g.
USE_ORIG_TEST_DRAM_BYTE. This will result in a cleaner code base with
parts of the code removed (dead code). Thanks for bringing this up.
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