[U-Boot] Pull request: u-boot-riscv/master

[uboot at andestech.com]

Hi Tom,

Please pull some riscv updates:

- sbi: Add newline to error message
- fu540: dts: Correct reg size of otp and dmc nodes
- Enhance reserved memory fixup about PMP information passed from OpenSbi
- sifive: fu540: Add gpio-restart support
- qemu: Add syscon reboot and poweroff support
- qemu-riscv: Update QEMU run command
- Assorted fixes related to reserved memory
- fu540: enable all cache ways from U-Boot proper
- use log functions in fdt_fixup

Thanks
Rick

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/703843003

The following changes since commit bcfe764ee925d0820e82c69ccf75b71d142644c7:

  Merge tag 'efi-2020-07-rc6-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-06-30 17:15:39 -0400)

are available in the Git repository at:

  git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to f889e3183a003e4e238f87cc9bb01bfcbd5548a5:

  riscv: use log functions in fdt_fixup (2020-07-02 10:31:39 +0800)

----------------------------------------------------------------
Atish Patra (2):
      riscv: Do not return error if reserved node already exists
      riscv: Use optimized version of fdtdec_get_addr_size_no_parent

Bin Meng (11):
      riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
      riscv: fu540: dts: Correct reg size of otp and dmc nodes
      riscv: Avoid the reserved memory fixup if src and dst point to the same place
      riscv: Expand the DT size before copy reserved memory node
      riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE
      sysreset: syscon: Don't assume default value for offset and mask property
      sysreset: syscon: Support value property
      riscv: Do not build reset.c if SYSRESET is on
      riscv: qemu: Add syscon reboot and poweroff support
      riscv: sifive: fu540: Add gpio-restart support
      doc: qemu-riscv: Update QEMU run command

Heinrich Schuchardt (1):
      riscv: use log functions in fdt_fixup

Pragnesh Patel (1):
      riscv: sifive: fu540: enable all cache ways from U-Boot proper

Sean Anderson (1):
      riscv: sbi: Add newline to error message

 arch/riscv/Kconfig                        |  3 +++
 arch/riscv/cpu/fu540/Makefile             |  1 +
 arch/riscv/cpu/fu540/cache.c              | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/dts/fu540-c000-u-boot.dtsi     | 10 +++++++---
 arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++++++++++
 arch/riscv/lib/Makefile                   |  2 ++
 arch/riscv/lib/fdt_fixup.c                | 46 ++++++++++++++++++++++++++++++++--------------
 board/emulation/qemu-riscv/Kconfig        |  4 ++++
 board/sifive/fu540/Kconfig                |  2 ++
 board/sifive/fu540/fu540.c                | 10 +++++++++-
 common/spl/spl_opensbi.c                  |  2 +-
 configs/sifive_fu540_defconfig            |  1 -
 doc/board/emulation/qemu-riscv.rst        | 10 +++++-----
 drivers/sysreset/sysreset_syscon.c        | 28 +++++++++++++++++++++++++---
 14 files changed, 158 insertions(+), 28 deletions(-)
 create mode 100644 arch/riscv/cpu/fu540/cache.c
 create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h