[U-Boot] Pull request: u-boot-riscv/next

[Tom Rini]

On Thu, Jul 02, 2020 at 09:50:53AM +0800, uboot at andestech.com wrote:

> Hi Tom,
> 
> This PR is for -next
> 
> Please pull some riscv updates:
> 
> - Add Sipeed Maix support
> - Update clock handler and proper cpu features
> 
> Thanks
> Rick
> 
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/703836681
> 
> The following changes since commit e2a4d24e6b1f3d30136e2dde7b6fbf35bd427b8a:
> 
>   Merge branch '2020-06-30-minor-TI-board-updates' into next (2020-06-30 15:03:25 -0400)
> 
> are available in the Git repository at:
> 
>   git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to add0dc1f7de91112d9e738f9482b09b75fa86acb:
> 
>   riscv: cpu: check and append L1 cache to cpu features (2020-07-01 15:01:27 +0800)
> 

Applied to u-boot/next, thanks!


-- 
Tom
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